Transcript Basic FPGA Configuration

Basic FPGA Configuration
Part 2
FPGA and ASIC Technology
Comparison - 1
© 2009 Xilinx, Inc. All Rights Reserved
Welcome
If you are new to FPGA design, this module
will help you understand the configuration
process and some more advanced features of
configuration
These configuration techniques apply to all of
Xilinx’s newest FPGAs, including Spartan-6
and Virtex-6
After completing this module, you will
able to:
Answer some Frequently Asked Questions
Describe the prototyping hardware currently available
Explain the role of each phase of the configuration
sequence
Connect multiple FPGAs into a configuration daisy
chain
Describe the features of the Xilinx Platform Flash and
Platform Flash XL
Question
Should my FPGA load its configuration data from an external memory or
should a processor or microcontroller download the configuration data?
The benefit of slave modes is that the bitstream can be stored pretty much
anywhere in your hardware system
Control logic can allow for in-system delivery of FPGA design updates
Additional components will have to be purchased
Debugging your custom control circuitry can be challenging
Master configuration schemes already have the control logic built inside of the
FPGA, so debugging is minimal
Always include a JTAG configuration path for easy debugging
FPGA and ASIC Technology
Comparison - 4
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2007 Xilinx, Inc. All Rights Reserved
Question
Should my system use a single FPGA or multiple FPGAs?
Most applications use a single FPGA
But some applications require multiple FPGAs for increased logic density
or I/O
Multiple FPGA systems should have a single configuration data source
and use a daisy chain
This reduces cost and simplifies programming and logistics
All of the configuration schemes support daisy chains
FPGA and ASIC Technology
Comparison - 5
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Question
Which is the simplest configuration scheme to debug?
Master Serial, BPI, and SPI modes are probably the easiest to use
Using any master configuration mode will be easy to debug because you
did not have to build the external control logic
Master modes use the fewest pins
Verses parallel modes which are the fastest, but have the most pins to
debug
SPI and BPI modes may also be least expensive
FPGA and ASIC Technology
Comparison - 6
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Question
Should I choose the lowest-cost configuration solution?
Do you already have a spare, non-volatile memory component in your
system?
The bitstream can be stored in system memory, on a hard drive, or
downloaded remotely over a network connection
Is there a way to consolidate the non-volatile memory required in your
application?
Can the bitstream of your FPGA be stored with any processor code for your
application (such as an embedded application)?
Can you use the SPI or BPI configuration schemes?
Because these devices have common footprints and multiple suppliers,
they may have lower pricing due to highly competitive markets
FPGA and ASIC Technology
Comparison - 7
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Question
Is the fastest possible configuration time the more important
consideration?
Parallel configuration schemes are inherently faster than serial modes
Configuring a single FPGA is inherently faster than configuring multiple FPGAs
in a daisy chain
In master modes, the configuration clock frequency of the FPGA can be
increased using the ConfigRate bitstream option
The maximum speed depends on the read specifications for the non-volatile
memory you have chosen
A faster memory can allow for faster configuration
The clock made by the FPGA varies by process. The fastest configuration rate
depends on this clock, so check your data sheet
If an external clock exists in your application, you can configure in slave mode while
using attached non-volatile memory
FPGA and ASIC Technology
Comparison - 8
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Question
Will the FPGA be loaded with a single configuration image or multiple
images?
Most applications use one image and the FPGA is configured when power is
turned on
Some applications re-load the FPGA multiple times, while the system is
operating, with different bitstreams for different functions (called MultiBoot)
For example, the FPGA can be loaded with one bitstream to implement a power on
self-test, followed by a second with the final application
In test equipment applications, the FPGA is loaded with different bitstreams to
execute hardware-assisted tests. With this method, one small FPGA can implement
the equivalent functionality of a larger ASIC or FPGA
The JTAG and slave modes easily support reloading the FPGA with multiple
images
However, reloading multiple images is also possible in Master schemes with the
newest FPGAs using the MultiBoot feature
FPGA and ASIC Technology
Comparison - 9
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Question
What I/O voltages are required in the end application?
The chosen FPGA configuration mode places some constraints on the
FPGA application—specifically the I/O voltage allowed on the
configuration banks of the FPGA
SPI and BPI modes leverage third-party Flash memory components that
are usually 3.3V-only devices
This requires that the I/O voltage on the banks attached to the memory also
be 3.3V
If a voltage other than 3.3V is required (this is the case with Virtex-6),
consider using a Xilinx Platform Flash PROM
Numonyx, Spansion, and Winbond are considering producing a flash
memory that is compatible with Virtex-6
FPGA and ASIC Technology
Comparison - 10
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Questions
Should the FPGAs I/O pins be pulled High via resistors during configuration?
Some of the FPGA pins used during configuration have dedicated pull-up resistors during
configuration
The majority of user I/O pins have optional pull-up resistors
Why enable the pull-up resistors during configuration?
Floating signal levels are a problem in CMOS logic systems
The internal pull-up resistors generate a logic High level on each pin
Similarly, an individual pin can be pull-down using an appropriately-sized external pull-down
resistor
Why disable pull-up resistors during configuration?
In hot-swap or hot-insertion applications, the pull-up resistors provide a potential current path to
the I/O power rail
Turning off the pull-up resistors disables this potential path
However, external pull-up or pull-down resistors are then required on each individual I/O pin
FPGA and ASIC Technology
Comparison - 11
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Question
Does the application target a specific FPGA density or should it support
migrating to other FPGA densities in the same package footprint?
The package footprint and pinouts for some Xilinx families are designed to allow
migration among different densities within a specific family
This may require a larger memory device
For example, three different Spartan™-6 LX FPGAs support the identical package
footprint when using the 256-ball fine-pitch thin ball grid array package FT(G)256
The smallest device, the XC6SLX4, requires approximately 2.5 Mbits for
configuration. The largest of these devices, the XC6SLX150T, requires
approximately 32.1 Mbits for configuration
To support design migration among device densities, allow sufficient configuration
memory to cover the largest device in the targeted package (remember to include
the size of any software)
FPGA and ASIC Technology
Comparison - 12
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File Generation
BitGen
Used to generate Xilinx FPGA bitstreams (.BIT) for configuration
Requires a native circuit design (.NCD), which is made after place and route has been
successfully completed
NCD defines the internal logic and interconnections for your FPGA design
iMPACT
GUI tool used to generate PROM Files
Used to configure FPGAs in-system, directly from a host-computer with a Xilinx download
cable
FPGA and ASIC Technology
Comparison - 13
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File Generation
PROMGen
Used to generate PROM Files
Formats a bitstream file (.BIT) into a PROM format file
Supports MCS-86 (Intel), EXORMAX (Motorola), and TEKHEX (Tektronix)
Can also generate a binary or hexadecimal file
FPGA and ASIC Technology
Comparison - 14
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Prototyping Solutions
Platform Cable USB
Low-cost JTAG/Slave Serial ISP cable
connects to USB port
Configures Xilinx FPGAs
Programs Xilinx CPLDs and PROMs
Platform Cable USB II
Low-cost JTAG/Slave Serial ISP cable
connects to USB port
Configures Xilinx FPGAs
Programs Xilinx CPLDs and PROMs
Programs SPI flash memory devices
Parallel Cable IV
Low-cost JTAG/SlaveSerial cable connects to
PC parallel port
Configures Xilinx FPGAs
Programs Xilinx CPLDs and PROMs
Note: Xilinx hardware solutions are not
recommended for production programming
FPGA and ASIC Technology
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Configuration Sequence
Steps are the same for all devices and modes
1) Device Power-Up
This timing diagram shows the first 3 steps of configuration
Check that your system powers-up the FPGA quickly enough
INIT_B is a bi-directional open-drain pin (external pull-up is required)
FPGA and ASIC Technology
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Configuration Sequence
2) Clear Configuration Memory
Configuration memory is cleared any time the device is powered up or after the
PROGRAM_B pin is pulsed Low
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There is a minimum length of time PROGRAM_B must be low
Can be held low as long as you want
After it is released the configuration memory is cleared twice
During this time I/Os are placed in a High-Z state
INIT_B is internally driven Low during initialization, then released after Tpor
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If INIT_B pin is held Low externally, the device waits at this point in the initialization process
until the pin is released
3) Samples Mode Pins
This is done when INIT_B goes HIGH
Then CCLK starts running
FPGA and ASIC Technology
Comparison - 17
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Configuration Sequence
4) Synchronization
For BPI-Up, BPI-Down, Slave SelectMAP, and Master SelectMAP modes, the bus width
must be first detected
A special 32-bit synchronization word (0xAA995566) is sent to the configuration logic
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This alerts to upcoming configuration data and aligns the configuration data with the internal
configuration logic
5) Check Device ID
ID check must pass before the configuration data frames can be loaded
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This prevents configuration with a bitstream that is formatted for a different device
If an ID error occurs during configuration, the device attempts to do a fallback reconfiguration
6) CRC (Cyclic Redundancy Check)
After the configuration data is loaded the configuration bitstream can issue a Check CRC
instruction to the device, followed by an expected CRC value
If the value does not match, the device pulls INIT_B Low and aborts configuration
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The CRC check is included in the configuration bitstream by default, but can be disabled
Intended to catch errors in transmitting the configuration bitstream
FPGA and ASIC Technology
Comparison - 18
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Configuration Sequence
7) Start-Up
The startup sequence is controlled by an 8-phase sequential state machine
The startup sequencer performs the following tasks (user selectable)
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Wait for DCMs to Lock (optional)
Wait for DCI to Match (optional)
Negate Global 3-state (GTS) (which activates I/O)
Release DONE pin (open-drain output requiring an external pull-up)
Assert Global Write Enable (GWE) (allows RAMs and FFs to change state)
Assert End of Startup (EOS)
–
Note that last 4 steps are default
FPGA and ASIC Technology
Comparison - 19
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What is a Daisy Chain?
Multiple FPGAs connected in series for configuration
Allows configuration of many devices from a single data source
Minimizes the board traces necessary
In our example, the first device in this serial daisy chain can be in any
configuration mode, but we chose the Master Serial mode
All other devices must be in Slave Serial mode
Note that additional configuration modes support daisy chains
Refer to the Configuration User Guide for your FPGA to learn about other
types of daisy chains
FPGA and ASIC Technology
Comparison - 20
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Creating a Serial Daisy Chain (Virtex-6)
First device is in Master Serial (000), second is in Slave Serial (111)
Connect all PROGRAM and CCLK pins together
Connect each DOUT to the DIN of the next device
Connecting INIT and DONE pins is recommended
FPGA and ASIC Technology
Comparison - 21
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Creating a Serial Daisy Chain (Spartan-6)
First device is in Master Serial (01), second is in Slave Serial (11)
Connect all PROGRAM and CCLK pins together
Connect each DOUT to the DIN of the next device
Connecting INIT and DONE pins is recommended
FPGA and ASIC Technology
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Creating a Daisy Chain
Connect PROGRAM pins
Required so that all FPGAs will all reprogram together
Connect CCLK pins
Required so that all FPGAs are synchronized with each other and with the
data stream
Connect each DOUT to the DIN of the next device
Required to allow each FPGA to receive the data stream
Connect INIT pins
Creating a single error flag is recommended
Connect DONE pins
Creating a single status flag is recommended
Connect DONE to the CE input of your PROM
FPGA and ASIC Technology
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How Does a Daisy Chain Work?
A synchronization word is passed to each device in the chain
The first FPGA in the chain is configured first
Keeps DOUT High until its configuration memory is full
Then data is passed to the next device in the chain
The startup sequence occurs after all devices are configured
FPGA and ASIC Technology
Comparison - 24
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XCFxxP Platform Flash Features
In-system programmable configuration PROMs
Ideal for smaller density FPGAs
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8, 16, and 32 Mb of in-system programmable flash storage
Multiple devices can be cascaded to configure larger FPGAs or multiple FPGAs daisy
chained together
Supports Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP
configuration modes
In-system programmable via JTAG
Data compression allows the user to target a smaller density Platform Flash
In Slave Serial mode the flash can generate its own configuration clock
1.8V supply voltage
FPGA and ASIC Technology
Comparison - 25
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XCFxxP Platform Flash Features
Design revisioning
Supports up to 4 unique design revisions
Customer example: safe updates
Rev0 is the golden image
Rev1 and Rev2 are new images
If Rev1 or Rev2 fail, Rev0 can be loaded automatically
REV0
REV1
REV2
REV3
Customer example: system tests
Rev0 is the board test
Rev1 is the production version
FPGA and ASIC Technology
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EN_EXT_SEL= 0
REV_SEL[1:0] = 01
Platform Flash XL Features
High Speed Storage Device (800 Mb/sec, 50 MHz w/16-bits)
Ideal for high density FPGAs, 128 Mb of in-system programmable flash storage
Supports 16 bit data bus
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Configuring at 30 MHz with a 16-bit data bus, a Virtex-6 LX130T device requires ~85 ms
to receive its 43 Mb of configuration data
Ideal for PCI Express and other high performance applications
Optimized for high-performance and ease of use
Standard NOR-Flash Interface for access to software code or data Storage
Supports MultiBoot bitstream for design revision storage
Can store data or processor code
Standard NOR Flash Interface
FPGA and ASIC Technology
Comparison - 27
Master SelectMAP Mode
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Platform Flash XL Features
Indirect programming of the flash can be done with a single cable
Configuration of the FPGA with the Platform Flash XL can be done with Master BPIUp, Slave-SelectMAP, or Master-SelectMAP modes
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Master-SelectMAP uses an internal configuration clock of 3 MHz
Slave-SelectMAP is the fastest
Special control of the power supply sequence or delay of the configuration process can
be required to ensure power-on readiness of the Platform Flash XL before the FPGA BPI
address sequence
Indirect programming of the
Platform Flash XL
FPGA and ASIC Technology
Comparison - 28
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2007 Xilinx, Inc. All Rights Reserved
Virtex-6 MultiBoot
MultiBoot is used for both fallback and warm boot reconfiguration
Fallback reconfiguration occurs when an error is detected during configuration
When fallback or IPROG occurs, a pulse resets the entire configuration logic
This reset pulse pulls INIT_B and DONE Low, and restarts the configuration
process
The FPGA drives new values on the two dual-mode pins RS[1:0] (Revision Select)
When a configuration error is detected, the configuration logic generates an internal
reset pulse and actively drives RS[1:0] to 00 to load the fallback (safe) bitstream
Warm boot (IPROG) reconfiguration is the same except the WBSTAR register
assigns RS
•
This is used to load a new bitstream at any time without powering down
Fallback Reconfiguration Usage for BPI
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* Initial Bitstream Selected as RS[01]
FPGA and ASIC Technology
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BPI Flash Address Space for MultiBoot
Spartan-6 MultiBoot
Spartan-6 MultiBoot is different from Virtex-6
Spartan-6 supports reconfiguration for
fallback and warm boot applications, but
cannot be activated by external pins (no RS
inputs)
With Spartan-6 the FPGA application
triggers a MultiBoot operation, causing the
FPGA to reconfigure from a different
configuration bitstream
There are three images for MultiBoot
configuration.
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The first image is the Header. This small
bitstream contains the syncword, sets the
addresses for the next bitstream as well as
the fallback or golden bitstream
The second image is the MultiBoot
Bitstream. This is the bitstream that the user
plans to configure first
The third image is the fallback or golden
bitstream. This bitstream is known to be
“safe” should an error occur consistently
during configuration
FPGA and ASIC Technology
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2007 Xilinx, Inc. All Rights Reserved
MultiBoot Logic
Summary
Master Serial, Master SelectMAP, SPI, and BPI are the simplest
configuration modes and take the least effort to debug
Slave configuration modes usually takes the most effort to debug
JTAG access enables much easier testing and debugging of prototype.
Multiple FPGAs can be connected to form a configuration daisy chain
The Platform Flash XL is designed to support Xilinx’s largest FPGAs and
is compatible with Virtex-6
FPGA and ASIC Technology
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Where Can I Learn More?
Configuration User Guides (from the ISE tools)
Help  Xilinx on the Web  (select a device family)  FPGA User Guides
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Virtex-6 FPGA Configuration User Guide, UG360
Spartan-6 FPGA Configuration User Guide, UG380
Virtex-5 FPGA Configuration User Guide, UG191
Platform Flash XL Configuration and Storage Device User Guide, UG438
Software Manuals (iMPACT, PromGEN, and BitGen)
Help  Software Manuals  Command Line Tool User Guide
Platform Cable USB II
Data Sheet, DS593
USB Cable Installation Guide, UG344
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Troubleshooting
BPI Programming Tutorial (evaluation kit page)
Help  Xilinx on the Web  Support & Services  Products & Services  Boards and
Kits  (select a board)  Documentation
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BPI programming tutorial for ML605 and SP601 demo boards
FPGA and ASIC Technology
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Where Can I Learn More?
Check out the Configuration Problem Solver
http://www.xilinx.com/support/troubleshoot.htm
This utility provides a step-by-step debugging guide for all configuration
schemes
Xilinx Training
www.xilinx.com/training
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Xilinx tools and architecture courses
Hardware description language courses
Basic FPGA architecture, Basic HDL Coding Techniques, and other Free
training videos!
FPGA and ASIC Technology
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2007 Xilinx, Inc. All Rights Reserved
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