Transcript DOH-MB - Indico

BPIX Supply Tube
Electronic Boards
Production and Testing Status
V. Fisch, T. Kiss, T. Tölyhi, V. Veszprémi
Status of the Prototypes
 The followin PCB of Slot 1 are already produced
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POH Motherboard (POH-MB)
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DOH Motherboard (DOH-MB)
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Aadapter Board (AB) L1&L2, AB L3&L4
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4 sets (4 pcs /each): Budapest, Aachen, Zürich, CERN.
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Connector Boards production stil have an issue
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Changed company two times
Only CB L3 and L4 have been submitted now to Exception PCB
Now Eception PCB is looking for a right production plant or partner to be involved
Alternative solution would be a fully polyimid board with exactly the same
thickness.
Flex cables are designed will be produced at Würth Elektronik
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We waited for the Adapter Boards the precise length verification
have to be ready together with the CBs
DOH-MB, DOH-MB, DOH, and POHs
mounted together
Testing of the Prototypes
DOH Motherboard
DOH-MB v1.2
AB L1&L2 - top
AB L1&L2 - bottom
Test Results of DOH-MB
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4 DOH-MB have been produced
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At the time of testing we had not had the POH-MB poduced yet
 The DOH-MB boards were first tested in themselves, powered up w/o the POH-MB
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For all 4 DOH-MB (8 fast I2C channels) we have the following
test results
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Bringing up the boards
 No shorts, power consumption are the same for all boards
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Configuring of the ASICs (throgh the slow I2C chain)
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We can access the two ASICs (PLL, DELAY25)
both ASICs respond with ACK,
we can enable/disable the DELAY25 outputs
we can set the delay values
Later these tests were repeated with a POH-MB as a carrier:
voltage supply and I2C configuration are still OK
Test Results of DOH-MB
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Functional tests
 The DOH-MB PLL locks to a 40 MHz input bit stream with
embedded trigger bits (TTC) generated by an FPGA board.
 we have the decoded clock (CLK) at the DOH-MB output,
 we have the decoded trigger (CTR) pulses at the DOH-MB output,
 we have the fast I2C data (SDA) at the DOH-MB output, and we also have
the regenerated clock for the return data (RCK) at the mDOH input.
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Summary
 No PCB or assembly issue
 We would like to keep 2 pcs for further testing – see next slide
 1 board to Zürich, 1 board to Aachen (if needed)
DOH-MB - Pending Tests
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The following tests have not been carried out yet
 Testing the signal integrity of the fast I2C signals through the entire
signal chain (from DOH-MB – flex cable - AB – CB)
 For L3&L4: two PCB routing options (selectable by jumper resitors) can
be tested
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Single long chain for L3 & L4 with one driver (1+1 Gatekeepers in total per DOH-MB)
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Two chains for L3 & L4 with two drivers (1+2 Gatekeepers in total per DOH-MB)
Jitter issue
 Use of QPLL is investigated (radiation tolerance?)
 new components placement and routing of the DOH-MB is needed
 DOH-MB v2
 The POH-MB was modified in the last minute that it can accomodate
a DOH-MB v2 (lock signals to CCU ring)
 We can/must start to work on a DOH-MB v2 before having the test results
and decision on the use of QPLL
Test Results of POH-MB
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4 POH-MB have been produced
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Latest modifcations
 Screw holes placement and implementation
 2 reserved signals (LOCK) between DOH-MB and CCU-ring
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For all 4 DOH-MB (8 fast I2C channels) we have
the following test results
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Connectivity test
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This time measured manually line by line
All 4 boards passed the tests
Possible issue: tracks very close to POH screw holes
These boards always have to be handled with extra care
(not to be bended)!
Pending tests
 fast data signal quality measurements at the end
of lines(at POH inputs). We would keep 1 board now.
 1 board to Zürich, 2 boards to Aachen (?)
Adapter Boards
AB L1&L2
AB L3&L4
AB L1&L2 - top
AB L3&L4 - top
AB L1&L2 - bottom
AB L3&L4 - bottom
Test Results of
AB L1&L2 and AB L3&L4
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4 - 4 AB L1&L2 and AB L3&L4 have been produced
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We have the following test results
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Connectivity test
 This time it was measured manually line by line
 All AB L1&l2, and 3 / 4 of the AB L3&L4 passed the tests
 On 1 board we have a short circuit, not found yet not even with a microscope
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it can be either under one of two connectors or inside the PCB
Low voltage (Vd and Va) voltage drop
 Important quantitative parameter of the AB and CB boards (just like of the
Extension Boards and modue cables): How we use up the voltage drop budget?
 See results in next slides
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Pending measurements
 No (Maybe more precise measurement of the GND plane resistance)
 AB boards have to be used in other pending measurements (fast I2C signal quality and
Sector C-D entire voltage drop) -> We keep 1+1 of them.
 1+1 boards to Zürich, 2+2 boards to Aachen (?)
Sector C: Va nd Vd voltage drop
simulations and measurements
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AB and CB voltage drop simulations
 In the PCB design phase, post-layout simulations were made for the forward
Va and Vd connections  iterating the „layout and routing” to minimize drop
 Common ground plane for the return path: resistance was estimated
 Both copper thickness, trace (plane) widthes, no. of layers (GND planes) are
all limited  We think that with the design efforts we went just to the wall.
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AB and CB voltage drop measurements
 Originally we wanted to measure it through the AdpterBoard – ConnectorBoard chain
(or even a module cable included), and this is what we have to do (will do) as soon as
we have all the boards.
 Now we measured the AdapterBoards only with the aim of verifying the simulations
 To get the whole voltage drop picture now, we have to rely on a mixture of
mesuremenst, simulations, and estimations, however the AdapterBoards
measurements can verify/correct the simulation results.
Sector C: Va nd Vd voltage drop
simulations and measurements
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AB and CB voltage drop simulations
 In the PCB design phase, post-layout simulations were made for the forward
Va and Vd connections  iterating the „layout and routing” to minimize drop
 Common ground plane for the return path: resistance was estimated
 Both copper thickness, trace (plane) widthes, no. of layers (GND planes) are
all limited  We think that with the design efforts we went just to the wall.

AB and CB voltage drop measurements
 Originally we wanted to measure it through the AdpterBoard – ConnectorBoard chain
(or even a module cable included), and this is what we have to do (will do) as soon as
we have all the boards.
 Now we measured the AdapterBoards only with the aim of verifying the simulations
 To get the whole voltage drop picture now, we have to rely on a mixture of
mesuremenst, simulations, and estimations, however the AdapterBoards
measurements can verify/correct the simulation results.
Sector C: Va nd Vd voltage drop
simulations and measurements
25,0
50,0
45,0
20,0
40,0
35,0
15,0
30,0
simulated
simulated
multimeter
multimeter
scope - avg
R 25,0
scope - avg
R
sim / multim
sim / multim
sim / scope - avg
sim / scope - avg
"1"
20,0
"1"
10,0
15,0
5,0
10,0
5,0
0,0
0,0
VA 1
VA 2
VA 3
VA 8
VA 9
VA 10
VD 1
net
AB L1&L2
VD 2
VD 3
VD 8
VD 9
VD 10
VA 4
VA 5
VA 6
VA 7
VA 11
VA 12
VA 13
VD 4
VD 5
net
AB L3&L4
VD 6
VD 7
VD 11
VD 12
VD 13
Sector C: Va nd Vd voltage drop
Pending Issues
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CB boards production to be completed soon
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Power cables to be designed and produced
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Verfication of the implemented delays vs. the detector needs
measure with the actual cable length distrubution
 Only minor changes is possible
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For the final production we need a scheduling for the deliver of
the boards (input from Lea till the beginning of summer)