Transcript Processor Register Set of M16C

Processor Register Set of M16C
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2 banks of general-purpose registers
4 16-bit data registers R0 - R3
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Upper and lower bytes of registers R0 and R1 can be used as 8-bit registers (R0L, R0H, R1L,
R1H)
2 16-bit address registers A0 & A1
Can access pairs of registers as 32-bit registers: R2R0, R3R1, A1A0
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Bank 0
Data register
Bank 1
PC
Program Counter
R0
R0H データレジスタ
R0L
R0
R1
R1L
R1H
INTB
Interrupt table register
R2 R1
R3 R2
R3Address register
A0
A1
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
SB
Static base register
アドレスレジスタ
A0
Frame base register
A1
FB
Frame base register
FB
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FLG
Flag register
1
Bus Slave Selection
Port enable (chip select)
 Only one slave device is active and accepts requests from the bus
 Decode address: get the most significant bits of the address
Memory Map
0x0000
Port enable
Master
Slave
Slave
CPU
Memory 1
Memory 2
EN
Address
Decoder
Memory 2
0x8000
“00” active
Address signal
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0x4000
EN
The upper 2
Chip Select
bits
16-bit
Memory 1
“01” active
0x1000 : 0001 0000 0000 0000
0x2000 : 0010 0000 0000 0000
0x4000 : 0100 0000 0000 0000
0x5000 : 0101 0000 0000 0000
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Peripheral Device: Control Register
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The control registers are used to set up different modes
 Some features are configured by separate bits
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The first step in programming peripheral devices is to understand control
registers of the device
Example of the configuration register
(M16C timer)
Name
Address
R/W
Access Size
Timer
A0 mode register
7
Timer A0 mode
register
0x0396
R/W
8
Timer A0 register
0x0387
R
16
Counter start flag
0x0380
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R
8
Counter source
select bit
6
TMOD0 TMOD1
5
4
3
2
1
0
MR0
MR1
MR2
MR3
TCK0
TCK1
Specify the operating mode
00: Timer mode
01: Event counter mode
10: One-shot timer mode
11: Pulse with modulation
(PWM) mode
Different
functions
depending on
the mode
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Peripheral Devices: Using the GPIO as an Output Port
Examples of HSB16C (speaker sound generators)
 1 LED is connected to port register, lights when 1 is written
LED4 lights in C
*((char*)0x03E0) = 0x01
M16C (microcontroller)
Address
Memory
CPU
Program
PC
0xF120
mov.b #1h, 03e0h
0xF000
Write memory
instruction
0xF120
VCC
GPIO
Port Registers
…01
LED4 : On
0x03E0
1
0
…
0
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1
LED3 : Off
1
4
Peripheral Devices: Using the GPIO as an Input Port
Examples of HSB16C
 The value of the port register is “1” when the switch is pressed.
Check SW9 in C
if(*((char*)0x03E1) & 0x20 == 0x20){… }
M16C
Address
0xF000
Memory
CPU
PC
0xF120
Read memory
instruction
Program
mov.b 03e1h, R1
0xF120
VCC
GPIO
SW9 : On
Port Registers
6
5
01
0
0x03E1
1
0
1
SW8 : Off
0
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1
GND
5
Peripheral Device: Pull-up and Pull-down
 High and low voltage values (Hi and Lo) are used to determine the ‘1’ and
‘0’ digital value
 Example: When the supply voltage is nearly 5v, 4 ~ 5v is Hi, 0 ~ 1v is Lo
 Digital signal voltage values must be in the range of Lo or Hi
 Pull-up and pull-down
 Circuit configuration for stable electrical input when connecting a switch to an input GPIO
port
Example of pull-up
Switch ON
Switch OFF
LSI
Vcc(5V)
LSI
Vcc(5V)
Port Register
ポートレジスタ
'1'
Port Register
ポートレジスタ
'0'
スイッチ
Switch
スイッチ
Switch
GND
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6
Peripheral Device: Serial I/O
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Set specific value to control registers to configure I/O port
Transmitter side: read value to send from special register, put it to transmit the
buffer
 Often FIFO is used
Receiver side: get received byte from buffer and put it to special register
To check if send or receive complete, check the status register
Receiver
Transmitting side
Control / status register
Control / status register
Receive buffer
Transmit Buffer
CPU
CPU
FIFO
FIFO
Transmission line
7 6 5 4 3 2 1 0
Shift register
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7 6 5 4 3 2 1 0
Shift register
7
Programmable Interrupt Controller (PIC)
 Accept multiple interrupt requests, issue a single interrupt request to a
processor
 Each interrupt request can be configured to be ignored
 Interrupt Source Register is used to determine what interrupt occurred
 Several PICs can be used in cascade
Get interrupt
information
Stores information
about interrupt
Source Register
PIC
Interrupt
enable/disable
Mask register
Interrupt request 1
CPU
Interrupt request 2
Interrupt request 3
Interrupt request 4
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