Transcript CPE 329 Rules!

Review for Midterm: CPE 329 Fall 2007
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Lectures 1-7, Chapters 1 & 2, Labs 1-2
Exam Review Outlines
Homework problems
ISE/EDK technology
Digilent Nexys board technology
– Not held accountable for specifics of Digilent D2FTDIO5 technology, just principles
• No coding, just pseudo code (no syntax)
• One side page of reference notes
• Calculator
Exam Review Outline: lecture 1
• Course Description
• Course Learning Objectives
• Topics Covered
• Prerequisite material
• Course Material
• Lab Overview
– Development Environment (CAD Tools)
– Lab Equipment
– Processor
• Lab Experiments
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Experiment 1
Experiment 2
Experiment 3
Experiment 4
Experiment 5
Hardware-Based Digital Clock
MicroBlaze “Hello World!”
Microcontroller-Based Digital Clock
Function Generator
Final Design Project
Exam Review Outline: lecture 2
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Taxonomy of Digital Systems
Advantages and Disadvantages of each category (Cost,
performance, ease of design, customization, configurability,
integration, number of transistors)
Semiconductor Technology Trends
Moore’s Law Number of transistors per die doubles every
couple of years (historical data)
http://www.intel.com/research/silicon/mooreslaw.htm
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ITRS Future Projection
Increase in the number of practicing engineers per year
Must work at higher levels of abstraction
Increasing levels of abstraction for HW and SW
Hardware Software Co-design
Homework
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4.
a.
b.
5.
6.
In class we talked about field and factory programmable gate arrays. Which type of gate
array would have better performance? State the two primary reasons given in class that one
will perform better than the other.
Hardware-based implementations typically have a performance benefit over stored-program
digital systems. Explain why this is true?
Given that hardware-based implementations typically have a performance benefit over
stored-program digital systems give three reasons that most embedded systems use either
microprocessors or microcontrollers?
VHDL Alarm Clock
Using the clock you designed for lab 1 we would like to add an alarm function. The system
requirement for the alarm function is to use another pushbutton to enter alarm mode. In alarm mode
the alarm time should be displayed on the LCD and the hours and minutes pushbuttons should
advance the hours and minutes of the alarm setting just as it did while setting the clock. There will be
a module that asserts a logic signal called BUZZ if the current time matches the alarm time.
Reusing the modules that you used for lab 1 (Time_Keeper, Arbiter, and HEX2BCD as shown in the
figure on the following page) draw a hardware diagram with the additional modules needed to add the
alarm function and briefly describe (1-2 sentences / module) how each block should function.
In the first lab many students noticed that it was cumbersome to set the clock if the minutes
and hours incremented every second during the set function. Determine how to have the set
function increment every 0.5 seconds. Assume that you are supposed to minimize the
changes to your current design and you can only use one system clock. Be sure to describe
the conditions that are needed to increment the seconds, minutes, hours, and am/pm when
in timekeeping mode.
In the lab we designed a Digital Clock using VHDL that was clocked with a 50MHz Epson
oscillator. The frequency tolerance for the oscillator is: ∆f/f = +/- 50x10-6. Explain what
are the sources of error in your digital clock and determine the maximum error that the clock
would have after running for 1 day.
Homework
7.
VHDL Design: Analyze the following VHDL code to answer the questions below:
entity state_machine is
port(
clk,S
: in std_logic;
z
:out std_logic );
end state_machine
architecture design of state_machine is
signal NS : std_logic_vector ( 1 downto 0) :=”00”;
begin
synch_proc:
process (clk, S)
begin
if (clk’event and clk=’1’) then
if(S=0) then
if (NS = “00”) then NS <= “01”;
elsif(NS = “01”) then NS <= “10”;
elsif(NS = “10”) then NS <= “11”;
elsif(NS = “11”) then NS <= “00”;
endif;
endif;
endif;
end
process synch_proc;
z <= NS(1);
end design;
a. Draw the State Diagram for the VHDL code:_________________________________
b. Complete the ModelSim simulated output for the state_machine circuit.______________
c. Describe the function of the state_machine circuit? ____________________________
Homework
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In the “Introduction to Digital Systems” chapter of the supplemental material
digital systems were first divided into two different categories. List the two
categories and identify which one generally has higher performance. Also explain
why this type of digital system has higher performance?
Does a factory programmed gate array or a field programmable gate array
typically have better performance? List two factors that contribute to a
performance advantage of one over the other.
You are asked to implement an algorithm using the tools available to you in the
CPE 329 lab. The application requires the highest-performance design that you
can download into the Digilent D2FT board. You notice that the algorithm is
computationally intense but does not have a significant amount of inherent
parallelism. Describe which approach and design tool you would select. Also,
explain why you chose this approach.
Does a factory programmed gate array or a field programmable gate array
typically use more silicon die area to implement a given VHDL design? List two
factors that contribute to a area advantage of one over the other.
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Exam Review Outline – lecture 3
• History of Integrated Circuits
• Advantages of CPLDs
• Programmable Elements to connect nets or configure hardware devices
– One-time-programmable (OTP) – Fuse/Antifuse
– Re-programmable
• Volatile (SRAM)
• Non-Volatile (EEPROM, Flash)
• CPLD Architecture Functional Blocks
– SPLD like configurable logic
– MacroCell
– MacroBlock
– Programmable Interconnect
– I/O Blocks
• FPGA Architecture
– FPGA Fabric
• Configurable Logic Block (Programmable MUX, Look Up Table, Pass Transistor)
• Programmable Interconnect
• I/O Blocks
• Block RAM Memory
• Hardcore blocks (ie Multipliers, PowerPC)
– System on Chip (Soc) using Hardcore or Softcore Processors
Exam Review Outline
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Programmable Interconnect (6-transistor junction)
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Propagation delay timing for interconnect 1st order model
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Design Example of 8-bit Ripple Carry Adder
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Direct – CLB to CLB
Local
Global
Timing – Clock networks
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Wired interconnect tPLH
Programmable interconnect tPLH
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CPLD Design
• Full Adder
FPGA Design
• 2-bit adder subcomponent
• LUT programming (Combining LUTs for more input variables)
• Programmable interconnect
Adder Using VHDL
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Exam Review Outline
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Design Flow
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Designer
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CAD Tool
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Write HDL Code
Simulate
Constraints
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Synthesis
Translate/Map
Place and Route
Generate Programming File
Download bit file
Xilinx FPGA and CPLD
Note: emphasis on Spartan 3
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Spartan IIE FPGA Architecture
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CoolRunner XPLA3 Architecture
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FPGA Fabric
I/O Block
CLB and CLB Slice
Product Family
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Features
Architecture Block Diagram
PLA Logic Inputs
Logic Block (MacroBlock)
I/O Cell
MacroCell
Timing Model
Homework
1.
In class we talked about the migration from discrete logic to CPLDs. State three advantages
of using CPLDs over discrete components.
2.
Explain the three ways that SRAM cells are used to configure the Xilinx Spartan2e FPGA.
3.
Calculate the fall-time for the Driver inverter in the circuit below whose output is routed
through the programmable interconnect on an FPGA. Use the values supplied in the table to
approximate Rp, Rn, and CL. Use the following definition of fall time: The time from when
the input changes from a low to high logic value to the time when the output reaches
0.1Vdd. (Note: ln(0.1) ≈ -2.3, ln(0.9) ≈ -0.1).
‘1’
Driver
Vin
‘1’
Component
Load
Vout
Value
Rp
22 kΩ
Rn
11 kΩ
CL
1x10-15 f
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Map the combinational function, F(X2,X1,X0)=X2 XOR X1 XOR X0, to the macroblock given
below. Assume an anti-fuse programmable element in the AND-array and denote a grown
fuse with an ‘X’. Indicate the configuration memory required such that F is routed as an
output to the I/O pin in the figure. Assume an SRAM-based programmable element (shaded
boxes) for the MUX control and use the following notation: 1 = logic high, 0 = logic low, and
D = don’t care.
global OE
1
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X0 X1 X2
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D Q
Clock
to AND
array
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s0
s1
F
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(a) Given the programmable interconnect structure shown below identify the best routing
from the output of CLB 1 to the input of CLB 8 to achieve the minimum interconnect delay.
Do so by darkening the best route you determined. All of the programmable interconnects
shown use the same type of pass transistor. You can assume the resistance in the wire is
approximately zero.
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A
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(b) What circuit parameters affect the interconnect delay?
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One student in a prior class asked how are the “System Gate Equivalents” determined for
FPGAs since a configurable logic block uses look up tables not logic gates for computation.
Estimate how many “System Gate Equivalents” one LUT has given the following data from
the Xilinx Spartan-2E Spec. Assume that all of the LUTs in an FPGA count for 10% of the
System Gates.
Device
XC2S300E
System Gate Range
93K – 300K
Total CLBs
1,536
Slices/CLB
LUT(16x1b)/Slice
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Exam Review Outline – lecture 4
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Computer Systems, Processors, and Terminology
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Custom HW – ASIC, VLSI, …
Processor vs. Microprocessor
Microcomputer vs. Microcontroller
Embedded system design process
Requirements
Specifications
Architecture
Components
System Integration
Embedded System
Characteristics: Complex Algorithms, user interface, real-time, multi-rate
Costs: Cost of goods, mfg cost, development cost
Challenges
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Hardware performance vs. Cost
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Code Space/ Code Density
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Need to meet real-time demands
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Minimize power consumption
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Design for upgrade-ability
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Verification
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Reliability
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Exam
Review
Outline
Embedded Systems Continued
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Computer System Block Diagram
System on Chip –SoC
Processor in ASIC or FPGA with Softcore processor
Programmers model – Registers, Condition Codes and Instruction Set
Architecture
Why is it important to know ISA?
Computer Classification
Architecture
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Von Neuman / Princeton Architecture
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Harvard Architecture
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DSP’s
RISC vs. CISC
EDK computer system
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MicroBlaze Processor
Busses (ILMB, DLMB, IOPB and DOPB)
MicroBlaze Memory System
Memory Controllers and BRAM
Memory Mapped I/O
IP Cores
GPIO Programming Input and Output Devices
Exam Review Outline
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Base Address
Memory Mapped Registers (Data Register and Data Direction Register)
I/O Instructions
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Software functions to read and write MicroBlaze memory locations
Xio_In32( ); and Xio_Out32( );
DIO5 I/O Controller (principles only)
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Bus Based Interface Between FPGA and I/O Controller
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Computer System
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Bus Write Cycle
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Timing Diagram
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Algorithm to implement using GPIO and MicroBlaze
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DIO5 Memory Map of I/O Devices
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LCD initialization Routine
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LCD Display Characters
Nexys interface to LCD and peripherals (buttons and leds)
Homework
1.
Microcontrollers are often a hybrid of RISC and CISC architectures. List the characteristics
discussed in lecture for each below?
2.
At the hardware level how would the MicroBlaze CPU set an 8-bit GPIO peripheral to be an
input? Describe what happens at the hardware level between the CPU and the GPIO
peripheral and NOT the device driver function call.
3.
Describe the uses of and differences between the OPB and the LMB busses?
4.
The Spartan IIe that we are using in the lab has 8k words of BRAM memory. The BRAM is
dual ported and has an address space of 0x0000 - 0x1fff. If the Instruction Memory
Controller base address is set to 0x0000 and the base address for the Data Memory
Controller is set to 0x1000 determine:
a.
What physical address would be read if the MicroBlaze fetched an instruction from
address 0x0100?
b.
What physical address would be read if MicroBlaze fetched a data operand with data
address of 0x1200?
Homework
6.
The following code is similar to the code in the blinker tutorial and shows how to set the
lower 8 LEDs on the DIO5 board. Show how the code should be changed to read the lower 8
pushbuttons and store the result into the pb variable.
Xuint32 XGpio_DiscreteRead (XGpio *InstancePtr, unsigned Channel)
Read state of discretes for the specified GPIO channnel.
Parameters: InstancePtr is a pointer to an XGpio instance. Channel contains the channel of the GPIO (1 or 2).
Returns: Current copy of the discretes register.
#define
#define
#define
#define
BtnLowAddr
BtnHighAddr
LedLowAddr
LedHighAddr
0x00
0x01
0x00
0x01
main(){ XGpio led_gpio, data_gpio, addr_gpio, cs_gpio, oe_gpio, we_gpio;
unsigned pb;
XGpio_Initialize(&data_gpio, XPAR_DIO_DATA_DEVICE_ID);
XGpio_Initialize(&addr_gpio, XPAR_DIO_ADDR_DEVICE_ID);
XGpio_Initialize(&cs_gpio, XPAR_CS_N_DEVICE_ID);
XGpio_Initialize(&oe_gpio, XPAR_OE_N_DEVICE_ID);
XGpio_Initialize(&we_gpio, XPAR_WE_N_DEVICE_ID);
XGpio_SetDataDirection(&addr_gpio, 1, 0);
XGpio_SetDataDirection(&cs_gpio, 1, 0);
XGpio_SetDataDirection(&oe_gpio, 1, 0);
XGpio_SetDataDirection(&we_gpio, 1, 0);
XGpio_SetDataDirection(&data_gpio, 1, 0);
XGpio_DiscreteWrite(&oe_gpio, 1,1);
XGpio_DiscreteWrite(&cs_gpio, 1,0);
XGpio_DiscreteWrite(&we_gpio, 1,0);
XGpio_DiscreteWrite(&addr_gpio, 1,LedLowAddr);
XGpio_DiscreteWrite(&data_gpio, 1,0xAA);
XGpio_DiscreteWrite(&we_gpio, 1,1)
XGpio_DiscreteWrite(&cs_gpio, 1,1);
}
Homework
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14.
What type of applications would benefit from a processor with a Harvard architecture?
Explain how the application benefits from a processor with a Harvard architecture.
Describe the uses of and differences between the OPB and the LMB busses?
Draw a timing diagram that shows a read of the lower 8 pushbuttons through the DIO5 I/O
Controller. Include all of the logic signals that connect to the DIO5 Board. You can assume
that the pushbutton 4 is pushed and the rest of the pushbuttons are not pressed.
What is the difference between a Harvard and Von Neumann/Princeton architecture? What
type of architecture does the MicroBlaze use?
MicroBlaze Memory System: Draw the architecture of the MicroBlaze memory system used in
Experiments 2 and 3. Provide values for base address registers where applicable.
I/O Controller Bus Cycles: In Experiments 2 and 3 you configured the MicroBlaze system
with five GPIOs for the data bus, the address bus, and three control signals to communicate
with the I/O Controller programmed in the CoolRunner CPLD on the DIO5 board. Write a C
function turn_on_leds() that will turn on all 16 LEDs on the DIO5 board using this same
MicroBlaze system. The header file for the xparameters.h and the DIO5 Default Circuit
Memory Map are provided on the next page.
In Experiments 2 and 3 you configured the MicroBlaze system with five GPIOs for the data
bus, the address bus, and three control signals to communicate with the I/O Controller
programmed in the CoolRunner CPLD on the DIO5 board. Write a C function
display_message() that will write “CPE 329!” to the LCD screen. on the DIO5 board using this
same MicroBlaze system. You may call the function configure_LCD() to initialize the LCD
screen and configure it for entry mode. You can use the header file xparameters.h
provided for lab 2 and 3.
You need to select either a PowerPC (RISC) or Motorola 68000 (CISC) microcontroller for a
particular design application. Both have adequate performance and comparable cost. The
application will require external memory so minimizing the code space is critical. Which
microcontroller will you select? Explain why you selected the microcontroller that you did.
Homework
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Ace engineer proposes writing a high performance OPB bus. Ace’s goal is to create an OPB
bus equivalent with all of the same functionality as currently is available but allow single
cycle bus transactions. Are these goals feasible? If so, describe one way the OPB bus
performance can be improved.
If our development board was running at 100MHz and the Xio_Write32() and Xio_In32()
functions calls only take one clock cycle to execute, then would we need to make any
changes in our bus read cycle code? Refer to the information in the DIO5 reference manual?
You are asked to add a second DIO5 board to the lab setup so that you have two LCD
displays to output messages. Now you are required to write “Hello World!” onto one
screen as before, and write “CPE 329 Rules!” on the other LCD Screen. Your design
requirements include using the fewest number of Slices and Code space as before.
a. Draw the system architecture for the new system. Be sure to include the number
of bits for each GPIO device.
b. Describe how the code would have to change to accommodate the new hardware
system and requirements as compared to the default computer system in the
tutorial. Your answer can be in bullet format but you must use sufficient detail to
carefully describe the software algorithms.
Given the MicroBlaze memory map used in the blinker tutorial for the computer system write
the minimum amount of “C” code to only light the lower four LEDs on the DIO5 board. Do
not use any pound defined words in your code (use hex numbers for function parameters) or
assume any initialization has been done.
Exam Review Outline – lecture 5
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Embedded Developers Kit Design Flow
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Hardware System
Add Cores
Bus Connection
Memory Map
Port Connections
Parameters
User Constraints
Software System
Device Driver Interface (Xio_Out, Xio_In, …)
Main Code using “C”
Compile
Generate Bitstream
Update Bitstream
Download code
EDK Nexys Tutorial
Homework
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3.
When using the EDK explain what happens when you execute
the following commands?
a. Generate Netlist?
b. Generate Libraries?
c. Update BitStream?
Describe what happens in the mapping stage of the Hardware
design flow? Describe what the input is for the mapping process
and what is generated by the mapping process.
You are asked to implement an algorithm using the tools
available to you in the CPE 329 lab. The application requires the
highest-performance design that you can download into the
Digilent D2FT board. You notice that the algorithm is
computationally intense but does not have a significant amount
of inherent parallelism. Describe which approach and design tool
you would select. Also, explain why you chose this approach.
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Exam Review Outline – lecture 6
• MicroBlaze
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Programmers Model
Data Types
Instruction Set
Program Counter and Machine State Register
General Purpose Registers
Instruction formats
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Overlapped execution
Performance (Latency, throughput, IPC, and CPI)
MicroBlaze Pipeline (F->D->Execute)
Data Dependency Hazards
Control Hazards
Delayed Branches
• Big Endian / Little Endian
• Pipelining
Exam Review Outline – lecture 7
Interrupts
• Asynchronous event that allows device to interrupt CPU and transfer control over to an interrupt
service routine.
• Foreground task (main loop)
• Interrupt Service Routing (ISR) or Interrupt Handler
• Interrupt and Acknowledge
• Hardware interface for interrupt
• Interrupt process at HW level
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CPU Initializes and enables interrupt device and unmasks interrupts
External Interrupt request generated
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CPU typically finishes current instruction
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Some CPU’s perform HW context save (if not context save is responsibility of ISR)
CPU’s typically disable interrupts automatically
Return address stored (on stack or in dedicated register)
Branch to interrupt service routine: Fetch Interrupt Vector (address of interrupt service routine) or address of instruction
in Jump table and put this address into the PC
Execute the interrupt service routine
ISR must clear interrupt flag (acknowledge interrupt)
Restore Context if not handled in HW
RTI - Return from interrupt instruction :Restores CPU context including condition codes and Branches to return address
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Possibly on chip peripheral device
Possibly external device
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Some instructions are interruptible
Debugging with interrupts
Multiple Interrupts and Interrupt Priorities
Maskable vs. Non-Maskable interrupts
Handling multiple interrupts using an OR gate
Interrupt controllers and multiple interrupt devices
Interrupt overhead
Comparison of Interrupts to Polling algorithms
Homework
1.
Determine the number of cycles from the time the first SUB instruction is fetched until the
last BNE instruction completes execution and the CPI for the following MicroBlaze assembly
code if the BNE branch is taken 1 times? Assume the SUB instruction execution stage takes 1
cycle to execute and the BNE takes the number of cycles described in lecture.
Loop:
SUB r3, r3, 1
SUB r1, r1, 4
SUB r2, r2, 8
BNEI r3, loop_offset
2.
The semantics for the MicroBlaze Instruction BEQ and BEQD are both the same {if Ra=0:
PC:=PC + Rb}. What is the difference between the two branch instructions? When would
BEQD be used and why would it? Be specific.
3.
List three specific items that contribute to interrupt overhead.
4.
Explain why the EDK has an Interrupt Controller IP Core? Be certain to discuss the
advantages that the Interrupt Controller IP Core would have compared to the simple “OR”
gate approach discussed in lecture.
5.
Determine the state of the carry bit and the Registers R1, R2, and R3 after the following
MicroBlaze assembly instruction is executed if R1 = 0x0f000000, R2 = 0xff000000, R3 =
0x8f000000 and C=0 before the instruction is executed. Also show the RTL description of
the instruction.
ADDKC R1, R2, R3