Transcript Folie 1 - RWTH Aachen University

Requirements for an
Outer Tracker Power System
and First Conclusions
Katja Klein
1. Physikalisches Institut B
RWTH Aachen University
Tracker Upgrade Power WG Meeting
June 4th, 2009
Preface
• This is not a proposal for a power system
• Objective is to summarize available relevant information
and start to understand consequences
• This talk is meant to trigger a discussion (today and during
next couple of months)
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Outline
• Short introduction of three main strawman layouts
• Total power consumption and conversion ratio
• Cable specifications and conversion ratio
• GBT
• Bias current and voltage
• CMS Binary Chip
• Implementation of a DC-DC buck converter
• Discussion of options for DC-DC conversion
• Conclusions
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Track Trigger
• We think we need to provide information from the tracker to the L1 trigger
• This leads to a very different tracker
• Large power consumption (see later)
• Two methods; both discriminate between low and high transverse momentum tracks
Cluster width
Stacked modules
G. Parrini, F. Palla (TWEPP2007)
J. Jones (~2005)
CMS Tracker SLHC Upgrade Workshops
α
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“Hybrid Strawman“
• Two trigger layers with stacked modules at 25cm and 35cm
Pixel size 100m x 2.37mm; dstack = 2mm
• Outer tracker similar to today, but shorter strips (4.5cm)
• 11 million strips, 300 million pixels (in the simulation)
• Outer tracker FE-power ~ 24kW
(reminder: strip tracker today needs 33kW for FE + links)
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“Long Barrel Double Stack Strawman“
• Whole tracker built of pixel modules with trigger capability
• 3 full + 2 short superlayers of double stack modules
• Pixel size 100m x 1mm
• No end caps
• FE-power ~ 100kW
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[Cluster Width Approach]
• 4 barrel layers, starting at 45cm radius (+ end caps)
• Short strips (2.5cm, 4.5cm)
• Must be combined with yet to be defined inner layers
• FE-power ~ 21kW four 4 barrel layers only
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Comparison of Layouts
Layout
FEPower
Link-Power Total Power
# of
Modules
FE-Power
per module
Long barrel double
stack (M. Mannelli)
100kW
25kW $
125kW
20 000
4 - 9W
Hybrid
tracking 12.5kW 2.9kW &
layout §
15.6kW &
(D. Abbaneo) trigger 12kW
43kW
10 040
0.94 - 1.9W
1 568 *
1.3 – 9W #
[Cluster width °]
(F. Palla)
23.2 – 35.0kW
14 037
1.25W
20.9kW 2.3 –
14.1kW %
All power numbers include a DC-DC efficiency of 80%
§ Variant with 2 long barrel pT layers and tracking-only endcaps
° Only four barrel layers, inner layer starting at 45cm
$ assuming 10Gb/s GBT-like link, 2W per link
& with 2W/GBT
% depends on optical module (GBT vs. MZM), larger number for GBT (3W per GBT)
* for A = 85cm2
# depends strongly on module proposal
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Total Power Consumption
• Total power consumption limited by heating up of water-cooled cable channels
• Today the total current in cable channels is 15kA
• Upper limit would have to be determined by measurements on mock-ups of
hot spots in cable channel (Hans Postema)
• 10-20% more might be possible, but probably not more? (Hans Postema)
• Can calculate maximum power consumption for certain convertion ratio r = Iin / Iout:
E.g. for r = 1/10 and 80% efficiency: Pmax = 150kA x 1.2V x 0.8 = 144kW
• Can estimate the necessary conversion ratio for a given power consumption:
r = 15kA / Iout
P = Uout x Iout (includes already converter efficiency of 80%)
r = 15kA x Uout /P
Katja Klein
Layout
Total Power
Operating voltage
Conversion Ratio
Long barrel
double stack
125kW
0.9V
1/10
Hybrid
strawman
43kW
1.2V
0.4
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Specs of Low Impedance Cables
• The 1944 Low Impedance Cables (LICs) must be re-used
• Low voltage conductor: 50 enamelled wires of 0.6mm2 in 2 concentric layers
• 10 twisted pairs (AWG26) at the centre: 5 x HV, 2 x sense, 3 x (T,H)
• 13nH/m, 7nF/m, Z0 = 1.4
• Specification of LV conductor: Umax = 30V, Imax = 20A (return)
• Specification of twisted pairs: Umax = 600V, Imax at least 0.5A (Simone Paoletti)
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Specs of PLCCs
• 356 standard multiwire cables, now used for control power
• Slightly different design for TIB/TID (# = 120), TOB (# = 92), TEC (# = 144)
• E.g. TEC: 2 twisted pairs (AWG28), LV: 2 x AWG14 (43x0.25mm) = 2 x 2.11mm2
• Specs for LV: Umax = 30V, Imax = 15A for TEC and 20A for TOB/TIB (S. Paoletti)
• We can probably not afford not to use these cables
TIB/TID
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TOB
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TEC
11
Conversion Ratio from Cable Specs
• Assume only 1 000 LICs can be used to power the modules (reason: next slide)
• Umax = 30V, Imax = 20A (return)
• Calculate mean number of modules per LIC
• Calculate mean current per LIC
• Estimate necessary conversion ratio
• In reality, could try to level out (but then granularity becomes an issue)
Layout
# of
Modules
Power per
module
# Modules Current per LIC Conv. ratio
per LIC
(worst case)
Long barrel double
stack
20 000
4 - 9W
20
200A
1/10
Hybrid
tracking
strawman
trigger
10 040
0.9 - 1.9W
12
19A
1
1 568
up to 9W
12
120A
1/6
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GBT
Transceiver: clock generator, de/serializer,
de/encoder, error correction...
Photodiode
Laser
Transimp. amp.
Laserdriver
Slow control ASIC
P. Moreia (ACES, Back-up slides, preliminary)
• Power per GBT = 2 – 3 W
• GBLD (450mW) & GBTIA (115mW) need 2.5V
• Other circuitry (~ 2.5W) needs 1.2V
• Two converters needed per GBT?
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Powering the GBT
• In many proposals, GBT components are placed outside of sensitive volume
 mass/space less of an issue
• Number of GBT links needed depends on proposal
Example hybrid layout: ~ 7 500 GBT links (Duccio):
 1 GBT per module for trigger  6 272 GBT links
 1 GBT per rod for readout of outer barrel layers
 36 GBTs per disk for readout of endcaps
 2 GBTs per rod for readout of trigger layers
• How many GBT links per power cable? Granularity/safety issue!
• Recall: we have ~ 2300 (LIC + PLCC) cables for GBT + module power
• Assume per power cable: 10 GBTs (modules) for trigger, 2 GBTs (rods) for readout
of outer tracker, 4 GBTs (2 rods) for readout of trigger layers: 1 127 GBT power lines
• This leaves us with ~ 1 000 power cables for the modules
• Do we really want to put 7 500 (x2?) DC-DC converters on the bulkhead or PP1?
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Bias Current & Voltage
• Assume again 1 000 LICs, each with 8 HV groups = 8 000 HV groups
 Today 4 HV lines share the return line
• Granularity similar to today, up to 10 modules per return line
• Current spec (0.5A) should be ok (next slide)
Katja Klein
Layout
# of
Modules
<# Modules> per
HV-Channel
Long barrel double
stack
20 000
2.5
Hybrid
tracking
strawman
trigger
10 040
1.5
1 568
1.5
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Bias Current
Alberto Massineo
Example:
A = 10cm x 10cm = 100cm2
100mA
10mA
1mA
 For R > 18cm current is
< 10mA per 100cm2 sensor
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Bias Voltage
PET von Y. Unno (KEK)
n-in-p Flowzone irradiation
G. Casse, A. Affolder
• Charge collection increases with bias voltage  do we need bias voltages > 600V?
• Not excluded, but would require careful tests & re-qualification of cables
• Atlas: have 2000 TRT cables which can stand 1kV; are considering piezo-electric
step-up converters and installation of additional HV-cables
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CMS Binary Chip
• Vana = 1.2V
• Probably Vdig < Vana (~ 0.9V)
• P = 64mW per Chip (26mW analog power, digital power ~ halved with 0.9V)
• Both analog and digital currents ~ 21mA per chip
• Shaping time 20ns  highest noise sensitivity around 8MHz
 low DC-DC switching frequency preferred
• Input voltage required to be  5% of nominal
• How to provide the two voltages? To be better understood.
 Use the two LV conductors in LICs and two separate buck converters
 Provide one input voltage, use two separate buck converters
 Derive Vdig from Vana with linear regulator (efficiency?)
 Derive Vdig from Vana with charge pump (ratio 4:3)
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CMS Binary Chip
 1000e
Spice simulation (Mark);
large pulse = 4fC (25 000e)
small “pulses“ due to
converter ripple;
no external filtering
10mV
Output ripple on 2.5V;
measured in Aachen
• Ripple of Aachen PCB with Enpirion chip measured with active differential probe
• Introduced noise of ~ 1000e is of same order as FE-noise  not acceptable?
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Integration of Buck Converters
Aachen PCB:
~ 1cm
~ 3cm
CERN PCB (proposal):
INDUCTOR
SMD
ASIC
SMD
SMD
SMD
1.5-2 cm
1.5-2 cm
 Space (currently) needed per buck converter: 2-4cm2
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Outer Tracker Module Proposal
• Duccio Abbaneo, Frank Hartmann, Karl Gill
TCS I/O PLL
2 x 4-MUX + LCDS driver
each output 160Mbit/s
DC-DC
shielded micro-twisted pairs I/O
DC-DC out 2.5V
Sensor HV
Sensor with 4x2.5cm strips
2x 1024 @95um pitch
integrated pitch adaptor
• 2 x 5cm or 4 x 2.5cm strips
• Integrated pitch adapter
• 6 or 12 CBCs
• Per CBC: 2 x 128 channels
• CBC-power ~ 0.75W per hybrid;
i.e. 0.75W or 1.5W per module
• Plus DCU, PLL, DC-DC inefficiency,
GBT-port, MUX, LCDS-driver
• No motherboards
• Upper part of hybrid ~ 2.5cm x 1cm,
no space for buck converter available
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2.5cm
8x CBC 2x 128ch
wire bonded
40Mbit/s out each
DCU
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Vertically Integrated Hybrid Module
Proposal by M. Mannelli et al.
Katja Klein
• Module for double stack proposal
• Modules integrated onto “beams“
• Sensor area = 85cm2
• 90nm
• Communication through vias in
ROC and interposer (3D-integration)
• No motherboards
• FE-power 4-9W per stacked module
• Up to 10A per stacked module
• Charge pumps no option
• Two buck converters per stack
• No space on module; no hybrid
• Integrate buck converters into
beam structure
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Trigger Module
Proposal by S. Marchioro
1 Modul:
• For pT-layers in hybrid layout
• 90nm
• Sensor size = 4.8cm x 4.8cm
• Hybrid ~ 1cm x 4.8cm
• No space for buck converter
• Power per pT-module = 2.6W
• I per modul ~ 3A
• Single charge pump no option
• 170mA per chip but 90nm, no space
for capacitors etc.
1 Chip:
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Trigger Module
Proposal by G. Hall
data out
control in
26mm
80mm
• For pT-layers in hybrid layout
• Sensor size ~ 2.6cm x 8.0cm
• Hybrid ~ 1cm x 4cm
• Again no space for buck converters
• Power per pT-module ~ 1.3W
• Current per single module ~ 600mA
• Could imagine here one charge pump per module with r = ½
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Integration of Buck Converter
• There is a tendency to avoid motherboards at all
 Outer tracker module, vertically integrated double-stack proposal, others?
• This goes hand in hand with rather minimalistic hybrids of a few cm2
• All existing or planned buck converter PCBs need an area of 2 - 4cm2
• Suggestion: a separate buck converter PCB close to the module,
e.g. inside the beam (for double-stack approach) or on the rod/stave
 converter needs cooling contact – probably not too dificult then
 need short power cable between converter PCB and module
 Could/should be designed such that it fits with all proposals/applications:
 Version with 1.2V and 0.9V for CBC
 Version with two buck converters for high-power trigger modules
 Version with 1.2V and 2.5V for GBT, for PP1 or bulkhead
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Integration of Buck Converter
Arguments for buck converter on separate PCB, close to module:
• Very limited space on most proposed hybrids  size less critical
• Larger distance preferred for EMI anyway (also damping of ripple?)
• Converter development completely decoupled from hybrid and module development
 No common deadlines, can optimize converter design as needed (even late)
• Different hybrids for different module proposals  many groups involved
• PCB could be developed, manifactured and tested standalone
• Easier for cooling? (module cooling is difficult enough without converters)
Arguments for buck converter on the module/hybrid:
• Less mass (avoid connectors & connection between converter and module)
• Power regulation closer to FE-ASICs (only relevant if no LDO)
• Could have pluggable PCB on hybrid, but then connectors are needed (mass)
• Noise effects can be tested more easily (don‘t need additional PCB)
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Discussion
• Discuss in the following three scenarios
 Only charge pumps
 Only buck converter
 Two step scheme with both buck converter and charge pump
• Then some comments on charge pumps and LDO regulators
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Scenario A: Only Charge Pumps
• Avoid buck converters or place them further outside (TEC Bulkhead, PP1 ...)
• Use only charge pump, assume r = ½ or ¼
• Charge pump either per module or per chip (do not distinguish here)
Pros:
 Only one technology to deal with
 Do not need to find space for buck converter
 No radiated noise from air-core inductor
Cons:
 Some proposals need r ~ 1/10
 Some proposals need too large currents (must be <1A per charge pump)
 For r = ¼, special HV-tolerant semiconductor process needed (as for buck)
 Additional chip(s) plus capacitors on the FE-hybrid
 Regulation only on cost of efficiency; a LDO regulator is needed in addition
 Studies show that buck converter (r = 1/8) close to module saves material
 Scenario with charge pumps only no reasonable option
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Scenario B: Only Buck Converters
• Avoid the use of any charge pumps
• Assume buck converter close to the modules with r = 1/6 or smaller (as needed)
Pros:
 Only one technology to deal with
 No additional chips on the FE-hybrid
 No influence on FE-chip design/layout
 No need for additional regulation
 No switching device very close to or inside the FE-chips
Cons:
 Must provide relatively high conversion ratio in one step (efficiency, noise?)
 Need to find space for buck converter(s) on or close to the module
 Considerable lower complexity, few disadvantages
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Scenario C: Both Buck + Charge Pump
• Buck converter with r  ¼ close to module
• Charge pump with r = ½, either per module or per chip
Pros:
 Can switch off single chips
 Easy start-up, can power only the “controls“
Cons:
 Two technologies to deal with
 Has basically all disadvantages of both previous options
 Complex system; arguments should be compelling
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Integration of Charge Pump
Pro for separate charge pump chips (per module or per readout ASIC):
 No constrains of layout of readout ASICs
 No risk of substrate noise
 Same chip could be used with different FE-ASICs
 On-chip no option for highly integrated approaches (needs external components)
 More flexible: can be used with some proposals, omitted in others
 Could power also auxiliary FE-ASICs (PLL, DCU, ...)
 If one charge pump per readout ASIC:
 more capacitors
 possibility to switch off single readout chips
Pro for charge pump as part of readout ASICs:
 More integrated approach, no separate chips to be produced, tested, integrated
onto hybrid
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Integration of LDO
• A LowDropout Regulator (LDO) could be needed to
 filter ripple on the power line
(but new Aachen measurements show that filter can be just as good)
 regulate the output voltage of the charge pump, which has no own regulation;
neccessity depends on the requirements of FE-ASICs on the PS
 regulation needed only for analog part
• Efficiency loss of a few per cent
• Additional part in FE-ASIC (currently not foreseen)
• Needs to be radiation hard
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Conclusions
• Conversion ratio depends on proposal, between 1/2 und 1/10
• Buck converters cannot be avoided (but charge pumps can)
• No motherboards and no or very small hybrids
 integrate buck converter onto separate small PCB
• Must understand better if charge pumps are needed and gain experience
 Only experience: Aachen tests with LBNL charge pump: excessive noise
• Must understand better if an LDO is needed
• Many cables will be needed to power GBT
• Need input from sensor WG on bias voltage
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Next Steps
• Follow-up meeting with Federico (tomorrow)
• Power session in Tracker Upgrade Project Office (June 10th)
• Understand better the possible options: talk by Federico on maximum
conversion ratio, currents, efficiency etc. in next power WG meeting
• In the meantime: watch progress on proposals & start discussion
• Write up buck converter specifications
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