Transcript Electronic Engineering Final year project By Claire Mc Kenna

Electronic Engineering Final
Year Project 2008
By Claire Mc Kenna
Title: Point of Load (POL) Power Supply
Design
Supervisor: Dr Maeve Duffy
Project Outline
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Objective is to compare the industry used
Dc-Dc Voltage Regulator Module (VRM)
the (Interleaved Buck Converter) with a
conventional power converter.
Conventional power converter V.I Chips,
PRM and VTM made by Vicor Corporation.
Pre-Regulator Module (PRM) and Voltage
Transformation Module (VTM) chips.
Background
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Operating voltages for microprocessors are
getting smaller e.g. 1V.
At present the Intel Xeon (LV) processor
operates at 1.1V.
As the operating voltage is reduced the
current drawn is increased.
Higher current results in higher dissipated
losses in mosfets and copper paths.
Background
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As switching frequency increases, the
switching losses increase.
Vicor have proposed a high current low
voltage solution providing low voltage high
current (100A) direct from 48V input.
Compare the V.I chips and the alternative
solution under steady state and transient
load conditions.
Progress to Date
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Review of VRM issues for future microprocessor
requirements.
Research on the PRM and VTM V.I chips.
2008 Intel launch new 45nm microarchitecture
with energy efficiency technology, so far no
information on power requirements or VRM
design.
Review of Buck converter using Pspice.
Review of the Multiphase Interleaved Buck
Converter.
Progress to Date
Review of the Buck Converter
Using the parameters below Pspice was used
to simulate the transient and steady state of
the buck converter.
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M
L
2 2N7000/ZTX3
1
2
23.18nH
2
1
Vin = 12V
Vo = 1.3V
F = 500Khz
0
Io = 100A
 The duty cycle was found to be 0.108 and the period
2us.
L = 23.18nH and C = 1538.46uF
Vin
C
R
D
1
12Vdc
1538uF
0.013ohm
Progress to Date
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Vout was less than 1.3V due to the
switching losses and voltage drops from
the mosfet and diodes.
By varying the duty to 1.9us the highest it
would go 1V was obtained at the output.
The output current was reduced to 10A and
new inductor and capacitor values were
calculated.
Progress to Date
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Varying the duty to
0.156 the output
voltage of 1.3V was
obtained.
Current ripple was
calculated to be 9.97A
and the measured
value obtained was
9.996A.
1.5V
1.0V
0.5V
0V
0s
0.5ms
1.0ms
1.5ms
2.0ms
2.5ms
3.0ms
3.5ms
4.0ms
4.5ms
5.0ms
V(R1:2)
Time
30A
20A
10A
0A
0s
-I(R1)
20us
I(L1)
40us
60us
80us
100us
Time
120us
140us
160us
180us
200us
Progress to Date
Two phases of the interleaved buck was simulated.
 By driving the mosfets 1us apart introduces the
interleaving effect which is the ripple cancellation in
the output capacitor.
 The duty was adjusted
and the correct output
voltage and current was
obtained.
 Transient load change was also simulated.
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160A
120A
80A
40A
400us
-I(R1)
420us
I(L1)+ I(L2)
440us
460us
480us
500us
Time
520us
540us
560us
580us
600us
Project Plan
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Order the VI chips so testing can begin and
to compare with simulated results.
Review the circuit diagrams of VTM and
PRM and simulate in Pspice.
Magnetic component design of a suitable
inductor/transformer for both VI chips and
Buck Converter.
Build and test for both solutions.
Proposals (Time Scale)
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Now – Review of the PRM/VTM chips.
Feb - Magnetic component design for V.I
chips and Buck converter.
Late Feb/Early March – Build and test
magnetic components for both solutions.
March – Consider the implications of future
microprocessor requirements for magnetic
components.