Transcript Folie 1 - Server der Fachgruppe Physik der RWTH Aachen

Tracker Power System –
Requirements and Studies
Katja Klein
RWTH Aachen University
CMS Upgrade Workshop
May 14th, 2009
https://twiki.cern.ch/twiki/bin/view/CMS/SLHCTrackerPower
[email protected]
Outline
• Introduction & requirements
• Ongoing activities
• Open questions
• Next steps
• Summary & conclusions
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Motivation
• Increased granularity & functionality  increase of power consumption
• Lower operation voltage  larger currents for same power consumption
• Services must be re-used (P ~ I2)
• Decrease of material budget highly desirable
 Novel powering scheme inevitable for the tracker (strips & pixels)
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Powering Schemes
Two powering schemes are widely discussed in the SLHC community:
Serial Powering and Powering via DC-DC converters
Power Task Force recommendation (Jan. 09, chair P. Sharp):
“The ‘Task Force’ recommends that the baseline powering system for an upgraded
CMS Tracking system should be based on DC-DC conversion,
with Serial Powering maintained as a back-up solution. [...]
It is important that design decisions taken during this process do not preclude
reverting to the back-up solution at a later date.”
Converter C converts a “high“ DC input voltage to voltage needed by detector D (V0)
Conversion ratio r = V0 / Vin < 1
 Lower input currents and
power losses:
Pdrop = RcabI02r2
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Buck Converters
Inductor-based converters provide large currents and are very efficient
- the buck converter is often studied as the simplest inductor-based variant
Switching noise
Ferrites saturate for B > ~2T
 air-core inductor needed
Vin  12V
HV-tolerant
semi-conductor
technology needed
 radiation-hardness
radiates noise
Efficiency
Material budget
Schematic scheme of a buck converter
(feedback control loop not shown)
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bulky
Tracker Power System
Space constraints
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“Charge Pump“ = Switched Capacitors
In simple step-down layout: capacitors charged in series and discharged in parallel
 Iout = nIin, with n = number of parallel capacitors
Capacitors are external
space, mass (but less than coil!)
Efficiency
Many switches
noise, losses
No regulation
(costs efficiency)
Lowish currents
Must be rad.-hard and tolerate Vin
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Strip Power System Requirements
• Compatibility with both trigger and tracking layers
• A large conversion ratio (depends on tracker power consumption)
• Adequate efficiency (depends on r, but roughly > 80%)
• Provision of all necessary low voltages: Vana = 1.2V, Vdig ~ 0.9V, Vopto = 2.5V
• Provision of ~ 50mA per chip, i.e. ~ 1A per module for outer tracking layers
• Provision of up to several Amps for trigger modules (depends on module variant)
• Provision of sufficient bias voltage with sufficient granularity
• Must not compromise the noise behaviour of the system (depends on FE-PSRR)
• Compatibility with existing Low Impedance cables
 Low voltage: V < 30V, I < 20A; high voltage: V < 600V, I < 0.5A
• Must respect heat tolerance of cable channels
• Contribution to material budget as low as possible
• Must be small enough to fit (details depend on integration)
• Save operation & easy start-up of thousands of modules
• Include proper grounding and shielding strategy
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Power WG Activities
Topic / Scheme
Electronics development
System tests
Material budget
DC-DC conversion
(baseline
solution)
Non-isolated inductor-based:
CERN (technology, ASIC
development, simulation);
Aachen (PCB);
Bristol (air-core coil)
Aachen (strips)
Aachen
Transformer-based:
Bristol
Fermilab, Iowa,
Mississippi (pixels)
Charge pump:
PSI (pixels);
CERN (strips)
Piezo-electric transformer: Serial powering
(back-up solution)
(Fermilab)
Fermilab, Iowa,
Aachen
Mississippi (pixels);
Rochester? (strips)
Implementation
Karlsruhe (Powering via cooling pipes): on hold
Power supplies, cables: not covered
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Phase-1: Power to the Pixels
• Phase-1 pixel upgrade: 4 barrel layers and 3 end cap disks
 FPIX power system layed out for 3 disks, no problem
 BPIX: 1612W  2919W (for L = 21034cm-2s-1)
 cannot be supplied by current power supplies
• How to power this BPIX detector? Options being worked out by PSI
1. Modify & use existing CAEN power supplies (A4603)
Status: modified PS in hands, to be tested
2. Use switched-capacitor DC-DC converters (“charge pump“)
a. Both for analog & digital power, conversion ratio 1:2
Vana = 1.7V, Vdig = 2.5V  device in HV-tolerant semiconductor process
b. Only for analog power, conversion ratio 1:2
c. Derive Vana from Vdig with 2:3 converter (less cables and connectors);
in combination with modified PSs
Evaluation of options is ongoing, no conclusion yet
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On-Chip Charge Pump for Pixels
Discharging
Charging
• Prototype by PSI (`08)
• Conversion ratio 1:2
• Iout = 24mA (1 ROC)
phi 1
phi 1
VIN
C1
phi 2
• 0.25 m IBM CMOS
phi 1
C2
VOUT
• Ext. capacitors (10-100nF)
phi 2
• Test of noise behaviour with
ROC to be done
• Future options: version for 1 module (16 ROCs); ratio 2:3
cap- cap+
GND
VDD
del
Vout
SW1 SW2 SW3
clk
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GND
VIN
C1
phi 2
phi 1
C2
VOUT
phi 2
Output voltage ripple (f=4MHz, C=10nF)
f
[MHz]
P_SC
P_Ri
Pout
10
2%
14 %
84 %
20
4%
15 %
81 %
40
8%
18 %
74 %
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5 mV/div
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Pixel Power Distribution Studies
• Fermilab, Iowa, Mississippi
• Power distribution studies with pixel ROC (PSI46)
 (Commercial) inductor-based converters with various PCB-embedded inductors,
switched-capacitor regulators, Serial Powering Interface Chip (developed at Fermilab)
• CAPTAN DAQ system with daughter boards
for DC-DC conversion (ready) & Serial Powering
 flexible, powerful DAQ used during integration,
can read out 480 ROCs
• Measurements have just started
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Development of Converter ASICs
• CERN electronics group, F. Faccio et al.
• Buck controller ASIC in HV compatible AMIS I3T80 technology (0.35m CMOS)
 First prototype “AMIS1“ (summer 2008): working, but large switching losses
 Second improved prototype “AMIS2“ submitted, expected back in May 09
 Semiconductor technology is not sufficiently radiation hard
 Nevertheless the AMIS2 will be tested within CMS (RWTH Aachen)
AMIS2
Vin = 3.3 – 12V
Vout = 1.2, 1.8, 2.5, 3.0, 5.0V
Iout < 3A
fs = 400kHz – 3MHz
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Development of Converter ASICs
• Identification of a sufficiently radiation-hard technology is crucial!
• New semi-cond. technology: IHP (Frankfurt/Oder) SiGe BiCMOS (SGB25VD)
 Irradiation tests of single LDMOS transistors (N and P)
X-rays up to 350Mrad TID,
protons (24GeV) up to 1016p/cm2
 Sufficienctly rad-hard for r > 20cm
• Buck ASIC including all main features submitted by CERN to IHP last week
expected back in ~ August
• More irradiations planned by CERN electronics group (May/June):
 Various generations of IHP LDMOS transistors
 AMS 180nm LDMOS transistors
• Development of r = ½ charge pump in 130nm (CERN + external student)
 I = 60mA; developed for Atlas, but could also be used in CMS readout chips
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Strip Tracker System Tests
• Commercial buck converters used to systematically investigate effects on
CMS FE-electronics (Enpirion EN5382D: fs = 4MHz, Vin < 7V) (Aachen)
• Aspects studied: ferrite/air-core inductor, solenoid/toroid, Low DropOut reg., shielding
 Current FE-electronics is sensitive to conductive & radiated converter noise
 Improve PCB layout, develop efficient filtering and low mass shielding
(ongoing, report in June meeting)
--- No converter
--- Toroid converter
--- Toroid converter + 30m shield
--- Toroid converter + LDO
--- T. converter + LDO + 30m shield
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Simulation of Strip Material Budget
• Reduction of material is one of the main motivations for novel powering schemes
• Simulation of the effect of powering schemes on the MB in CMSSW (Aachen)
Total MB of:
TEC modules
TEC Converters
TEC electronics & cables: - 30.0%
Original TEC
TEC with
buck converters
r = 1/8
• Many options/layouts have been studied (position, 1-step/2-step, shielding, ...)
 Typical gain: ~20-30% for electronics/cables, ~5-7% for total MB
(Caveat: gain in motherboards is not only due to decreased current)
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Tasks / Open Questions & Next Steps: Pixels
• Phase-1
 How to power the pixel barrel detector during phase-1?
 Is a switched-capacitor converter needed?
 Various options being evaluated (PSI, 2009)
 Charge pump development has started (PSI)
• Phase-2
 Are additional buck-like converters on service cylinder needed?
 What is their effect on the pixel electronics?
 Investigation of powering schemes on ROC (US, 2009/10)
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Tasks / Open Questions & Next Steps: Strips
• Overall system layout must be defined, in particular
 conversion ratio (depends on tracker power consumption)
 1-step vs. 2-step scheme (depends e.g. on conversion ratio)
 # of converters/module (Vana, Vdig)
 integration onto module or motherboards (space, EMI, practicability, etc.)
 position of converter (close to module, or higher radii)
 bias voltage delivery (problematic, if > 600V are needed)
 integration of GBT components (2-3W, some parts need 2.5V)
• Specifications for ASIC & PCB, driven by tracker needs
 output voltage & current, conversion ratio, switching frequency,
tolerable noise level, minimal efficiency, tolerable dimensions etc.
 Intense discussion over next couple of months, taking into account the
recent layout developments/options
 Try to narrow down powering options and develop a consistent scheme
until autumn, to streamline powering R&D and guide other WGs
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Tasks / Open Questions & Next Steps: Strips
• Interplay with readout ASIC(s)
- PS rejection ratio, additional circuitry (regulators, charge pump)?
 To be understood/decided together w/ FE designers; discussion has started
• Cables (not covered)
• Power supplies (not covered)
• Performance of converter ASIC (efficiency, optimal layout (buck?) etc.)
 Development of custom buck converter prototypes (CERN, 2009/2010)
• Semiconductor technology
 Irradiation of transistors from IHP and AMS (CERN, until autumn 2009)
• Noise effects on CMS tracker structures
 System tests with converter prototypes (Aachen, 2009/2010)
 System tests with SLHC readout chips, hybrids, modules (Aachen, 2010 - ?)
• Integration of DC-DC converters into tracker system
 Developm. & optimization of PCB + inductor (Aachen, CERN, Bristol, 2009/10)
 Grounding & shielding, system design (> 2010, needs rod prototypes)
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Summary & Conclusions
• HV-tolerant rad-hard process identified  important step forward
• Development of buck converter ASICs progressing well
• Development of switched-capacitor chips started at PSI and CERN
• Understanding of noise issues progressing at several institutes
• Discussions during next couple of months should lead to a strip powering
scheme that obeys all boundary conditions and is technically feasible
• Iterate and converge towards Technical Proposals
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Back-up Slides
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R&D Proposals relevant for Power WG
07.01: R&D on Novel Powering Schemes for the SLHC CMS Tracker;
by RWTH Aachen (contact person: Lutz Feld), submitted in October 2007;
status: approved
07.08: R&D in preparation for an upgrade of CMS for the Super-LHC by UK groups;
by University of Bristol, Brunel University, Imperial College London, Rutherford
Appleton Laboratory (contact person: Geoff Hall), submitted in October 2007;
status: approved
08.02: An R&D project to develop materials, technologies and simulations for silicon
sensor modules at intermediate to large radii of a new CMS tracker for SLHC;
by University of Hamburg, Karlsruhe University, Louvain, HEPHY Vienna, Vilnius
University (contact person: Doris Eckstein), submitted in March 2008;
status: approved
08.04: Power Distribution System Studies for the CMS Tracker;
by Fermilab, University of Iowa, University of Mississippi (contact person: Simon
Kwan), submitted in June 2008;
status: approved
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Open Tasks
• Cables
 Understand consistency of LICs with new powering scheme
Looks ok except for bias voltage
 Understand how to integrate LICs into new scheme
 Cables from PP1 to detector need replacement
• Power supplies
 Very likely power supplies need to be exchanged
 Develop specs, identify and interact with company, test etc.
• Need to identify groups willing to take these responsibilities
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