Transcript SystemVerilog Enhancement Requests

SystemVerilog
Enhancement Requests
Daniel Schostak
Principal Engineer
February 26th 2010
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Contents
1. Introduction
2. Efficiency Enhancements
3. Expressiveness Enhancements
4. Construct / Language Enhancements
5. Examples of Ambiguities
6. Conclusion
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Introduction
 What is ARM’s interest in SystemVerilog?
 It is one of the Hardware Verification Languages that we use
 What does ARM use SystemVerilog for?
 Constrained Random Verification
 Functional Coverage
 High Level Assertions for Formal Verification
 What is my involvement with SystemVerilog?
 Co-developed methodology and associated internal class library for
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constrained random verification
Developer of constrained random SystemVerilog testbench
(execution unit for an ARMv7-A CPU)
Verification Lead for ARMv7-A CPU project with SystemVerilog as
main HVL from initial development to tape-out
Efficiency Enhancements
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Ability to copy pointers to arrays (currently have to wrap
array with class so can copy object handle)
Ability to copy pointers to functions (currently have to wrap
function with class so can copy object handle)
Ability to pass expressions to const ref function arguments
(extension of http://www.eda.org/svdb/view.php?id=2349)
If object being randomized contains empty list/null object,
constraints that would apply to objects in list/non-null object
should not be considered (cannot know what constraints
object instance itself would have)
Expressiveness Enhancements
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Chain function invocations
(http://www.eda.org/svdb/view.php?id=2735)
Allow declarations at any point in a block statement rather
than only at the beginning (otherwise end up creating
dummy block statements)
Use of new() in non-declaration contexts
(e.g. q.push_back(new) or q.push_back(new <T>))
new with { … } (otherwise have to explicitly create
constructor that provides this behaviour)
“others” in distribution constraints (otherwise end up
specifying blanket range including values already specified
hoping this does not skew distribution)
No specific order requirement for keywords in declarations
Class Construct Enhancements
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Some way of deriving class from multiple parents
 Aspect Oriented Programming
 C++ Multiple Inheritance
 Java style interfaces (class can implement multiple interfaces)
Some way to document and enforce overriding restrictions
 Parent class specifies derived class cannot override function
 Derived class specifies not overriding function in parent class
Parse function implementations in parameterized classes
only if implementation is used
Allow use of import with static identifiers declared in class
(e.g. enumerated type identifiers)
Friend classes
Provide equivalent of final block for class declarations
Hierarchy Related Enhancements
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Treat hierarchical references to parameter values as
elaboration time constants (facilitate parameter sharing –
see http://www.eda.org/svdb/view.php?id=1058)
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SystemVerilog event variable can be used as pointer to
Verilog static event (allows decoupling of hierarchy in
similar way to virtual interfaces)
Ability to refer to global namespace from inside package
(avoid package proliferation)
Ability to “import” signal declarations from scope bound to
(avoid explicit port list when binding module of assertions)
Allow use of modports when instantiating interfaces with
bind directives
Syntax for lexical scope references in bind directive
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Miscellaneous Enhancements
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Variable width part selects
(http://www.eda.org/svdb/view.php?id=2684)
Allow casting_type to be compile time constant expression
(in particular class parameter value)
Ability to use .* for parameter value assignments
(special case of http://www.eda.org/svdb/view.php?id=98)
Reopening of packages
(http://www.eda.org/svdb/view.php?id=2961)
System task for determining seed simulation started with
(useful for constructing unique file names)
More specific `__FILE__ type compiler directives
 `__CLASS__ in form of string literal
 `__FUNCTION__ in form of string literal
Examples of Ambiguities
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Elaboration order of bind directives (e.g. bind interfaces into
DUT and then reference bound interfaces in succeeding
bind directive; can also have effect on random stability)
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Format of $typename return value should be standardized
Order of randomization method invocations if randomizing
nested objects
Should default argument be repeated in class method
out-of-block declaration?
Result of $sformatf(“%0<n>b”, value) if value[<n-1>] === x
(is string representation padded with leading zero?)
Should .name() for escaped identifier include “\”?
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Should $value$plusargs(“<plusarg>=%s”, value) set value
to “” or “0” for +<plusarg>= / +<plusarg>=“”?
Conclusion
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Top Five Enhancements
1. Ability to derive class from multiple parents
2. Copy pointers to arrays
3. Expressiveness enhancements
4. Ambiguity resolution
5. Extend support for generic programming