Transcript Compiler Activities

CAPS
Compilers Activities
IRISA
Campus Universitaire de Beaulieu
35042 Rennes
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CAPS TEAM
• Architecture
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André Seznec (Director of Research, CAPS group leader)
Pierre Michaud (Researcher)
Jacques Lenfant (Professor)
Thierry Lafage (PhD)
Jonathan Perret (PhD)
Romain Dolbeau (PhD)
• Compiler
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F. Bodin (Professor)
Antoine Monsifrot (PhD)
Ronan Amicel (PhD)
Gilles Pokam (PhD)
Laurent Bertaux (PhD)
Laurent Morin (PhD)
Karine Heydemann (PhD)
Background
• Architecture
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high performance (co-)processors
superscalar microprocessors
memory hierarchy
branch prediction mechanism, ...
• Compiler
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high performance computing
parallel computing
optimizations for VLIW
preprocessor infrastructures
code transformations
Compiler Activities
• Code optimizations for embedded applications
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– infrastructures
– optimizing compiler strategies
• Global constraints
– code sizes
– low power (starting)
• Interactive tools
– code tuning
– case based reasoning
– assembly code optimizations
tool 1
Front-end
Interface
tool 2
Code
Generation
Target
Description(s)
feedback
tool 3
Back-end
Optimizer
tool 4
Instruction set
Simulator
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Provides tools for code tuning
– user oriented
– case based reasoning
– static code analysis and pattern matching
– profiling
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Infrastructure used
– Foresys: Fortran interactive front-end (from Simulog)
– TSF: Scripting language for program transformation (developed by CAPS)
program text
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Bibliography:
“FITS - A Light-Weight Integrated
Programming Environment”, B.
Chapman, F. Bodin, L. Hill, J.
Merlin, G. Viland, F. Wollenweber,
Euro-Par'99
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context variables
TSF scripts
script local variable stack
script global variables
scripts
apply
Foresys
display
program unit
symbol
table
var1
var2
var3
...
executable
statement
variable
declaration
scripts instructions
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Provide methods and tools for analyzing code quality and for fine grain
tuning
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VLIW architectures
navigation in the assembly code
access to profiling and compiler data
link with the source code
Infrastructure used
– Salto
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High Performance Instruction Set
Simulation
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Provide new generation techniques for instruction set simulation
– high performance, simulation of large code, debugging
– flexible
– retargetable, experiment new instruction sets
C Source
Architecture
tmcc
TriMedia Assembly code
generator
tmas
C++ Source
TriMedia Binary
gcc/ld
tmsim
description
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Infrastructure
– Salto
compile
simulation
• SALTO2
– provide new infrastructure better suited for code optimization
– more abstract interface
– more integration with code generation
Architecture
Description
Interfaces
Opt 1
Intermediate
Code
Text
Input
Architecture Model
D®M
P ® RI
Opt 2
Opt n
Intermediate representation
interface to IR
User interface
G.U.I.
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External
Infrastructure
D ® Ass
(Emit)
Optimized
Program
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Provide tools to help rewriting code source for exploiting multimedia
instructions
Declaration
Rules
SWARgen
SWARcc
AST
CCMIR
IR
Pattern
matching
Unparser
The SWAR SYSTEM
COSY
C Code
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Graph
rewriting
Dealing with global constraints
Better control of tradeoffs
2.85E+08
(S0,S0,S0,S0,S0)
MPEG-2
2.80E+08
(S0,S0,U2,S0,S0)
2.75E+08
Bibliography:
“Handling Global Constraints in
Compiler Strategy”, Erven Rohou,
François Bodin, Christine Eisenbeis
and André Seznec, to appear in
International Journal of Parallel
Programming
number of cycles
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(I,S0,S0,S0,S0)
2.70E+08
2.65E+08
(I,S0,U2,S0,S0)
2.60E+08
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(I,I,U8,U8,S0)
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2.55E+08
2.50E+08
2.45E+08
120
170
220
270
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370
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code size (instructions)
1.90E+08
H-263
1.80E+08
1.70E+08
2
number of cycles
Iterative Compilation
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1.60E+08
1.50E+08
1.40E+08
1
1.30E+08
1.20E+08
1.10E+08
1.00E+08
70
90
110
130
150
code size (instructions)
11
170
190
210