Transcript ppt

CS232: Computer Architecture II
Spring 2010
AMD dual-core Opteron
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Who we are
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Lecturer:
Prof. Viraj Kumar
Visiting Lecturer
[email protected]
Office hours: Friday 4pm to 5pm and by email, 2211 SC
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Teaching Assistants/Section Instructor: Room 0212 SC
Ryan Cunningham
Abner Guzman Rivera
Arushi Aggarwal
Pritam Sukumar
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[email protected]
[email protected]
[email protected]
[email protected]
Thu. Pm (lab)
Thu. Pm (lab)
Fri. 10-11am
Thu. 10-11am
MPs released on Friday, (usually) due next Friday
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Graded work
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Five or six MPs, builds towards SPIMbot Tournament, 25% of grade
— You can work individually, or in groups of 2 or 3
— Submit something that can be tested by the deadline
— I’ll email you feedback (using an auto-grader) within 24 hours
— You can resubmit for full credit 48 hours after the deadline
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Three Wednesday evening Midterms, 15% each
— Exam 1: 2/24 ; Exam 2: 3/17 ; Exam 3: 4/21 (tentative)
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Final, cumulative, date to be decided: 25%
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Section attendance: 5%
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What is computer architecture about?
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Computer architecture is about building and analyzing computer systems
HLL
Compiler
ASM
Processor
Memory
Input/Output
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Instruction Set Architecture is bridge between hardware and software
— Study the MIPS ISA in detail
— Learn what compilers do when they translate high-level code into
assembly (we won’t learn how they do it)
— Learn how HLL program constructs are represented to the machine
Key techniques: Pipelining, Caching, Virtual Memory
Tuning complex code for performance (course project)
Exploiting parallelism
Hey Prof. Kumar, Today I interviewed at Microsoft.
I referenced spimbot and used concepts learned in
class multiple times. I just wanted to say THANKS!
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Multi-Core Processors
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Two (or more) complete processors, fabricated on the same silicon chip
Execute instructions from two (or more) programs/threads at same time
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XBox360: 3 PowerPC cores
Sony PS 3: asymmetric 9 cores
IBM Power5
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Why Multi-cores Now?
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Number of transistors we can put on a chip growing exponentially
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Performance vs. Power trade-off
 Power has become a limiting factor for single cores
— hence multi-cores
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As programmers, do we care?
 What happens if we run a program on a multi-core?
void array_add(int A[], int B[], int C[], int length) {
int i;
for (i = 0 ; i < length ; ++i) {
C[i] = A[i] + B[i];
}
}
#1
#2
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Instruction set architectures
Software
ISA
Hardware
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The ISA is an interface between software and hardware
— the hardware “promises” to implement all ISA instructions
— the software uses ISA primitives to build complex programs
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The instruction set architecture affects the hardware design
— simple ISAs require simpler, cheaper processors
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Also affects software design
— simple ISAs result in longer programs
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Why MIPS?
 We study the MIPS instruction set architecture to illustrate concepts in
assembly language and machine organization
— concepts are not MIPS-specific
— MIPS is just convenient because it is real, yet simple (unlike x86)
 MIPS ISA is used in many places, primarily in embedded systems
— routers from Cisco
— game machines like the Nintendo 64 and Sony Playstation 2
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What you will need to learn for Exam 1
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You must become “fluent” in MIPS assembly:
— Translate from C++ to MIPS and MIPS to C++
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Example: Translate the following recursive C++ function into MIPS
int pow(int n, int m) {
if (m == 1)
return n;
return n * pow(n, m-1);
}
How are complex expressions
broken into simple instructions?
How are arguments passed?
How are values returned?
How is recursion done?
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MP 1: Gray codes
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A binary representation of integers, where successive integers differ in
exactly one bit
— the standard representation does not have this property
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For an integer n, let (n) denote the binary representation of n
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The gray-code representation of n is : (n)  ( n/2 )
— here, “” is bit-wise XOR and   is the floor function
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Example: gray-code(6) =
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MP 1: Gray codes contd.
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The gray-code representation of n is : (n)  ( n/2 )
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Note that n/2 = n  1 (right-shift)
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Example: gray-code(6) =
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