Transcript lec02

Instruction Set Architecture
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COMPUTER SYSTEM DESIGN
LECTURE 2
WHAT’RE THE COMPONENT OF ISA?
 Machine
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Instruction Set
 Instruction format
 Nature of the fetch through execute
VARIES PROGRAMMING MODEL
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WHAT MUST AN INSTRUCTION SPECIFY?
 Which
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Operation is perform?
ADD
r1,r2,r3
 Where to find the operands
ADD
r1,r2,r3
 Place to store the result
ADD
r1,r2,r3
 Location of next instruction
BASIC ISA CLASS
Accumulator (1 register)
1 address
add
1 + x address
addx
 Stack :
0 address
add
 General Purpose Register
2 address
add
3 address
add

tos <= tos + next
A, B
A, B, C
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A; acc <= acc + mem[A]
A; acc <= acc + mem[A+x]
BASIC ISA CLASSES(CON’T)

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Load/Store
load Ra, Rb Ra <= mem[Rb]
Store Ra, Rb
mem[Rb] <= Ra
COMPARE NUMBER OF INSTRUCTION
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Stack
Code Sequence for C = A + B
Accumulator
Register
Register
(reg. - mem)
(load/store)
Push A Load A
Load R1,A
Load R1,A
Push B Add B
Add R1,B
Load R2,B
Add
Store C
Store C, R1 Add R3,R1,R2
Pop C
Store C,R3
CPU REGISTER
Stack Register
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Arithmetic Register &
Address Register
GENERAL PURPOSE REGISTER
1975 - 1995 all machines use general purpose registers.
 Advanced of Registers
- faster than memory
- easier for compiler to use
- hold variables

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SUMMARY INSTRUCTION SET CLASS
Data Movement Instructions
- Load
- Store
 Arithmetic and Logic (ALU) Instruction
- Add, Sub, Shift …
 Branch Instructions
- Br, Brz, …

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3-ADDRESS MACHINE AND ISA
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2-ADDRESS MACHINE ISA
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1-ADDRESS MACHINE AND ISA
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0-ADDRESS MACHINE AND ISA
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EXAMPLES
stack
push b
push c
add
push d
mpy
push e
sub
pop a
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3-address
add a,b,c
mpy a,a,d
sub a,a,e
a = (b+c)*d - e
2-address
1-address
load a,b
load b
add a,c
add c
mpy a,d
mpy d
sub a,e
sub e
store a
REAL MACHINE

Have mixture of 3, 2, 1 or 0 address instructions
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if ALU instructions only use registers for operands and result,
machine type is load-store
 mix of register-memory and memory-memory

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BREAK 5 MINUTES
ADDRESSING MODE
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ADDRESSING MODE
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Addressing Mode Examples
Meaning
Register
Add r4,r3
r4 <= r4 + r3
Immediate Add r4,#3
r4 <= r4 + 3
Displacement Add r4,100(r1) r4 <= r4 + mem[100+r1]
indirect(r) Add r4,(r1)
r4 <= r4 + mem[r1]
index+base Add r3,(r1+r2)
r3 <= r3 + mem[r1+r2]
DirectAdd r1,(1001)
r1 <= r1 + mem[1001]
indirect(m) Add r1,@(r3) r1 <= r1 + mem[mem[r3]]
auto-incre Add r1,(r2)+ r1 <= r1+mem[r2];r2=r2+d
auto-decre Add r1,-(r2)
r2 <=r2-d,r1<=r1+mem[r2]
scaledAdd r1,100(r2)[r3]
r1 <=r1+mem[100+r2+r3*d]
MIPS REGISTERS
31 x 32-bit GPR (R0 = 0)
 32 x 32-bit FP register
 PC
 lo hi-multiplier output register

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R0
R1
PC
lo
hi
R31
MEMORY ADDRESSING

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Since 1980, Most machine uses address to level of
8-bits (byte)
How do byte address map onto words?
 Can a word be placed on any byte boundary?

ENDIANESS AND ALIGNMENT
Big Endian : 68k, SPARC, MIPS, HP PA
 Little Endian : 80x86,DEC(Vax, Alpha)

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GENERIC OF INSTRUCTION FORMAT WIDTH
Variable :
Hybrid :
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Fixed:
...
SUMMARY ISA
Variable length instructions, if code size is
very important.

Fixed length instructions, if performance is
most important.

Embedded Machine (ARM, MIPS) have optional
mode to execute 16-bit
wide.
(decide performance or density)
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
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TO BE CONTINUOUS
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PART II : LECTURE 2
MIPS ISA TARGET
Embedded System

used by NEC, Nintendo, Silicon Graphics,
Sony
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
MIPS ISA
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MIPS ADDRESSING MODES

All instructions have 32-bit wide.
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MIPS ARITHMETIC INSTRUCTION
Example
Meaning
add $1,$2,$3
$1 = $2 + $3
sub $1,$2,$3
-----------------$1,$2,100
-----------------addu $1,$2,$3
-----------------subu $1,$2,$3
-----------------addiu $1,$2,100 ----------------mult $2,$3
Hi,Lo = $2x$3
multu $2,$3
------------------
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Instruction
1.add
2.subtract
3.add imme addi
4.add unsign
5.
6.
7.multiply
8.
MIPS ARITHMETIC INSTRUCTION
Example
div $2,$3
10.
11.mov
12.
Divu $2,$3
mfhi $1
mflo $1
Meaning
Lo=$2/$3,
Hi=$2mod$3,
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Instruction
9.divide
MIPS LOGICAL INSTRUCTION
Example
and
xor
nor
andi
ori
xori
sll $1,$2,10
Srl $1,$2,10
Meaning
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Instruction
13.AND
14.OR
or
15.XOR
16.NOR
17.
18.
19.
20.shift left logical
21.
MIPS LOGICAL INSTRUCTION
Meaning
(sign extend)
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Instruction
Example
22.shift right arithm sra $,$2,10
23.
sllv
24.
srlv
25.
srav
MIPS DATA TRANSFER
INSTRUCTIONS
sw 500(r4),r3
Store word
sh 502(r4),r3
store half word
sb 41(r4,r3 store byte
lw r1,30(r2) load word
Lh r1,40(r2) load half word
Lb r1,40(r2) load byte
lui r1,40
load upper
immediate (16 bits shifted left by 16)
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26.
27.
28.
29.
30.
31.
32
TESTING CONDITION
Condition Code
add r1,r2,r3
bz
label
 Condition Register
cmpr1,r2,r3
bgt r1,label
 Compare and Branch
bgt r1,r2,label

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MIPS COMPARE AND BRANCH
Compare and Branch
BEQ
rs,rt,offset
BNE
rs,rt,offset
 compare to zero and Branch
BLEZ
rs, offset
BGTZ
rs, offset
BLT
<
BGEZ
>=
BLTZAL
if R[rs] < 0 then branch and link(to R31)
BGEZAL
>=

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MIPS JUMP, BRANCH COMPARE
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SOFTWARE CONVENTIONS FOR
REGISTER
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NOTE FOR MIPS INSTRUCTION SET
R0 always = “0” (even if u try to write)
 Branch/jump and link PC+4 ->R31
 Imme arith and logical are extended
- logical imme op are zero extend to 32 bits
- arith imme op are sign extend to 32 bits
 data loaded by lb, lh extended
- lbu, lhu are zero extended
- lb, lh are sign extedned
 Overflow occur in ADD, SUB, ADDI

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
Don’t occur in ADDU, SUBU, ADDIU, AND, OR, XOR,
NOR, SHIFT, MULT, MULTU, DIV, DIVU
MIPS ARITHMETIC
Instruction has 3 operands
 Operand order is fixed

a := b + c;
add $s0, $s1, $s2
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Pascal Code :
MIPS Code :
MIPS ARITHMETIC
Pascal Code :
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MIPS Code :
a := b + c + d;
e := f - a;
add $t0, $s1, $s2
add $s0, $t0, $s3
sub $s4, $s5, $s0
REGISTER & MEMORY

Registers were used in Arithmetic Instructions
- 32 registers
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MEMORY ORGANIZATION
Memory is an index into the array
 Byte Addressing = points to a byte of memory

8 bits of Data
8 bits of Data
8 bits of Data
8 bits of Data
8 bits of Data
8 bits of Data
8 bits of Data
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1
2
3
4
5
6
7
MEMORY ORGANIZATION
For MIPS, a word is 32-bit or 4 bytes
 232 bytes with byte addresses from 0 to 232-1
 230 words with byte address from 0, 4, 6, …,232-4

32 bits of Data
32 bits of Data
32 bits of Data
32 bits of Data
32 bits of Data
32 bits of Data
32 bits of Data
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0
4
8
12
16
20
24
MIPS LOAD/STORE INSTRUCTION
Arithmetic Operand is Register, not Memory!!
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Code
:
A[8] = h + A[8];
A[8] ==> 8 x 4 = 32 (word alignment)
MIPS Code
:
lw $t0, 32($s3);
add $t0,$s2,$t0;
sw $t0, 32($s3);
EXAMPLE :

swap:
lw $15, 0[$2]
lw $16, 4[$2]
sw $16, 0[$2]
sw $15, 4[$2]
jr $31
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Swap (int v[], int k);
{ Int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1]=temp;
}
MEANING
$2, $4, $2
$16, 0[$2]
$15, 4[$2]
$2 = $4 + $2;
$16 = Memory[0 + $2]
Memory[4+$2] = $15
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add
lw
sw
MACHINE LANGUAGE
Instructions, like register & words of data are
32 bits long.
- add $t0, $s1, $s2
- register : $t0 = 9, $s1 = 17, $s2 = 18
 Instruction Format

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MACHINE LANGUAGE
I-type for Data transfer instruction
 Example : lw $t0, 32($s2)

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CONTROL
Decision Making instructions
 MIPS conditional branch instructions:
- bne $t0, $t1, label
- beq $t0, $t1, label
 Example : if (i=j) h= i +j;
bne $s0, $s1, Label
add $s3, $s0, $s1
Label : ...

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CONTROL
MIPS unconditional Branch
 Example :
if ( i != j)
beq $s4, $s5, label;
h=i+j;
add $s3, $s4, $s5;
else
j
lab2
h=i-j;
lab1: sub $s3, $s4, $s5
lab2: …

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SUMMARIZE :
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HOMEWORK
1. “Factorial Program”
n is input, Example : if n=3,
result = 3! = 3 x 2 x 1 = 6
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Use MIPS Assembly to write program.
HOMEWORK
2. Write program that use Most of the
MIPS instructions
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Use MIPS Assembly to write program.
MIPS INSTRUCTION ENCODING
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Please see more detail in the
Figure 3.18