Transcript RISC Architecture

RISC Architecture
RISC vs CISC
Sherwin Chan
Instruction Set Architecture
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Types of ISA and examples:
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RISC
CISC
MISC
ZISC
SIMD
EPIC
VLIW
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Playstation
Intel x86
INMOS Transputer
ZISC36
many GPUs
IA-64 Itanium
C6000 (Texas Instruments)
Instruction Set Architecture
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CISC – Complex Instruction Set
Computer
RISC – Reduced Instruction Set
Computer
Problems of the Past
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In the past, it was believed that
hardware design was easier than
compiler design
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Most programs were written in assembly
language
Hardware concerns of the past:
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Limited and slower memory
Few registers
The Solution
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Have instructions do more work,
thereby minimizing the number of
instructions called in a program
Allow for variations of each instruction
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Usually variations in memory access
Minimize the number of memory
accesses
CISC
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Each instruction executes multiple low
level operations
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Ex. A single instruction can load from
memory, perform an arithmetic operation,
and store the result in memory
Smaller program size
Less memory calls
The Search for RISC
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Compilers became more prevalent
The majority of CISC instructions were
rarely used
Some complex instructions were slower
than a group of simple instructions
performing an equivalent task
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Too many instructions for designers to
optimize each one
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Smaller instructions allowed for
constants to be stored in the unused
bits of the instruction
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This would mean less memory calls to
registers or memory
RISC Architecture
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Small, highly optimized set of
instructions
Uses a load-store architecture
Short execution time
Pipelining
Many registers
Load/Store Architecture
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Individual instructions to store/load
data and to perform operations
All operations are performed on
operands in registers
Main memory is used only to load/store
instructions
RISC vs CISC
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Less transistors needed in RISC
RISC processors have shorter design cycles
RISC instructions take less clock cycles than
CISC instructions
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CISC instructions take up to 3 to 12 times longer
Smaller instructions allowed for constants to
be stored in the unused bits of the instruction
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This would mean less memory calls to registers or
main memory
MIPS: A RISC example
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Smaller and simpler instruction set
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111 instructions
One cycle execution time
Pipelining
32 registers
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32 bits for each register
MIPS Instruction Set
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25 branch/jump instructions
21 arithmetic instructions
15 load instructions
12 comparison instructions
10 store instructions
8 logic instructions
8 bit manipulation instructions
8 move instructions
4 miscellaneous instructions
Pipelining 101
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Break instructions into steps
Work on instructions like in an assembly
line
Allows for more instructions to be
executed in less time
A n-stage pipeline is n times faster than
a non pipeline processor (in theory)
MISC/RISC Pipeline Stages
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Fetch instruction
Decode instruction
Execute instruction
Access operand
Write result
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Note: Slight variations depending on
processor
Without Pipelining
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Normally, you would peform the fetch,
decode, execute, operate, and write
steps of an instruction and then move
on to the next instruction
Without Pipelining
Clock Cycle
Instr 1
Instr 2
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2
3
4
5
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9
10
With Pipelining
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The processor is able to perform each
stage simultaneously.
If the processor is decoding an
instruction, it may also fetch another
instruction at the same time.
With Pipelining
Clock Cycle
Instr 1
Instr 2
Instr 3
Instr 4
Instr 5
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2
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4
5
6
7
8
9
Pipeline (cont.)
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Length of pipeline depends on the
longest step
Thus in RISC, all instructions were
made to be the same length
Each stage takes 1 clock cycle
In theory, an instruction should be
finished each clock cycle
Pipeline Problem 1
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Problem: An instruction may need to
wait for the result of another instruction
Ex:
add $r3, $r2, $r1
add $r5, $r4, $r3
………
Pipeline Problem 1 (cont)
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Solution: Compiler may recognize which
instructions are dependent or
independent of the current instruction,
and rearrange them to run the
independent one first
Pipelining Problems 2
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Problem: A branch instruction evaluates
the result of another instruction that
has not finished yet
Ex: Loop :
add $r3, $r2, $r1
sub $r6, $r5, $r4
beq $r3, $r6, Loop
…………
Pipelining Problems 2 (cont)
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Solution 1: Guess. Begin on predicted
instruction first. If wrong, clear pipeline
and begin on correct instruction.
Ex: For a loop statement, assume it will
loop back, because the majority of the
time it will.
Some processors remember old
branches and use that to predict new
ones
Pipelining Problems 2 (cont)
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Solution 2: Begin decoding instructions
from both sides of the branch. After the
branch is evaluated, send the correct
instructions to the pipeline.
How to make pipelines faster
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Superpipelining
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Divide the stages of pipelining into more
stages
Ex: Split “fetch instruction” stage into
two stages
Superduperpipelining
Superscalarpipelining
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Run multiple pipelines in parallel
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Dynamic pipeline: Uses buffers to hold
instruction bits in case a dependent
instruction stalls
Why CISC Persists
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Most Intel and AMD chips are CISC x86
Most PC applications are written for x86
Intel spent more money improving the
performance of their chips
Modern Intel and AMD chips
incorporate elements of pipelining
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During decoding, x86 instructions are split
into smaller pieces