Transcript Omar Hernandez RISC

RISC
By Omar Hernandez
CS147
Types of CPUs
 CISC
 RISC
Types of CPUs
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Complex
Instruction
Set
Computers
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
Reduced
Instruction
Set
Computers
CISC
 Have large instruction sets that are close to
higher language structures
 Examples of CISC:
– Intel’s Pentium- class CPUs
– Motorola 68000 CPUs
RISC
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Reduced
Instruction
Set
Computing
RISC
 Instruction set for RISC processors are:
– Simple
– Pure Assembly language dedicated to the
design of the CPU
RISC Features
 Fixed length Instructions
 Limited Loading and Storing Instructions
Access Memory
 Fewer Addressing Modes
 Instruction Pipeline
 Large Number of Registers
 Hardwired Control Unit
RISC Features (Cont’d)
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Delayed Loads and Branches
Speculative Execution of Instructions
Optimizing Compiler
Separate Instruction and Data Streams
RISC Instruction Sets
 In general have only up to 100 instructions
in their set
 Each instruction is capable of being
executed in a single clock cycle
RISC Instruction Sets (Cont’d)
 Basic Instructions include:
– Data move (load, store, & register move)
– Arithmetic
– Logic
– Shift
– Branch (jumps)
RISC Instruction Sets (Cont’d)
 RISC CPUs operate usually on two data
types:
– Integer
– Floating point
 Using different precisions or numbers of bits
within a given data type
 Using these basic data types, you can
program into more complex data types
RISC Instruction Sets (Cont’d)
 RISC CPUs use different instruction formats
 Every instruction must have same amount of
bits regardless of format
 CPU must be able to access each
instruction code in a single memory-read
operation in order to facilitate pipelining
RISC Instruction Sets (Cont’d)
 Instruction set usually has different types of
load and store due to bit alignment using
from
– 8 bit
– 16 bit
– 32 bit
– Etc.
RISC Instruction Sets (Cont’d)
 Addressing modes all depend on clock cycle
– Without it you would have to redesign pipeling
used to process instructions
RISC Instruction Sets (Cont’d)
 RISC II CPUs have:
– 3 primary memory addressing modes
– Indexed address mode
– Register indirect address mode
– Contain a pseudoregister R0 that’s always zero
RISC Performance
 RISC uses two techniques to improve
performance:
– Instruction Pipeline
– Register Window & Renaming
RISC Performance (Cont’d)
 Instruction Pipeline
– Breaks down fetch-decode-execute process into
several instructions in parallel
– Pipeline allows one instruction per clock cycle
Instruction Pipeline
Instruction Pipeline (Cont’d)
Instruction Pipeline (Cont’d)
Instruction Pipeline (Cont’d)
Instruction Pipeline (Cont’d)
 Speedup is the ratio of time needed to process n
instructions using nonpipelined control unit to the
time needed using a pipelined control unit with the
following formula:
nT1
Sn 
(n  k  1)TK
Instruction Pipeline (Cont’d)
 T1 is
time needed to process 1 instruction
using a nonpipelined control unit
 k is number of stages in pipeline
 TKis clock period of the pipeline
 Example:
n 180ns
180
Sn 

 3.6ns
(n  4  1)  50ns 50
Instruction Pipeline Requirements
 RISC CPU must include cache memory that
is at least as fast as the pipeline
 Cache must separate instructions and data
to avoid memory conflicts from stages of
pipeline
 Compiler has to be optimized to reorder
instructions in order to avoid problems with
branch instructions
Register Windowing & Renaming
 Takes advantage of large amounts of
registers that RISC CPUs have
 Producing more hits to register than memory
 Thus producing faster CPU performance
Types of registers
 Global register – always accessible
 Windowed register – a subset accessible at
any specific time
MIPS register organization
Register Renaming
 Makes use of any group of register with
pointers
 Doesn’t follow a register convention which
assigns registers to a certain task
Instruction Pipeline Conflicts
 Data Conflicts
– Software fixes
 No-op insertion
 Instruction reordering
– Hardware fix
 Stall insertion
 Data forwarding
 Branch Conflicts
Data Conflicts
No-Op Insertion
Instruction Reordering
Stall Insertion
Data Forwarding
Branch Conflicts
 Solutions
– No-op insertion
– Instruction reordering
– Annulling
– Branch prediction
Branch Conflicts (Cont’d)
 Annulling
– Instructions proceed through the pipeline as
they normally would. If an instruction should not
have been executed, because a previous
instruction branched away from it, its results are
not stored.
Branch Conflicts (Cont’d)
 Branch Prediction
– Allows the compiler or pipeline hardware to
make an assumption as to whether or not the
conditional branch will be taken.
RISC vs. CISC
 Each type of processor has its benefits
 Depends what type of device to be built
 If it’s a small device
– RISC
 If it’s a large device
– CISC