Transcript Document

Part 1

Intel x86/Pentium family


SUN SPARC and UltraSPARC


32-bit CISC processor
32- and 64-bit RISC processors
Java


C  C++  Java
Why Java?
 Binaries are not portable nor can they be secured
 Complexity of C++

Java

How?
 Bytecode (for hypothetical machine)
 Moved around the web
 Interpreted by JVM (Java Virtual Machine)
 32-bit w/ 226 instructions (some complex)
 JIT compilation

SUN Pico Java II family of chips




No JVM
Optional cache and fp unit
Example is micro Java 701
Used by embedded systems

CPU


Bus


Central Processing Unit
collection of (parallel) wires for transmitting address,
data, and control signals
Instruction format

opcode [operand1,…]
 Opcode = operation code (e.g., add)
 Operand = (optional) data upon which opcode is performed
(e.g., add 12,r0 – add 12 to register 0 – 12 and r0 are the
operands)
The organization of a simple computer with
Tanenbaum, Structured Computer
Organization,
Fifthtwo
Edition, (c)
2006
one CPU
and
I/O
devices
Pearson Education, Inc. All rights
reserved. 0-13-148521-0
1.
CU = control unit
2.
ALU = arithmetic logic unit
3.
Registers = small amount of high speed
memory
1.
CU = control unit

Fetches instruction from main memory and
determines their type
2.
ALU = arithmetic logic unit
3.
Registers = small amount of high speed
memory
1.
CU = control unit
2.
ALU = arithmetic logic unit

3.
Performs operations such as add, subtract, or, etc.
Registers = small amount of high speed
memory
1.
CU = control unit
2.
ALU = arithmetic logic unit
3.
Registers = small amount of high speed memory
stores temp results and control info
 holds (only) one number
 PC = program counter

 points to next instruction to be executed

PS = processor status (EFLAGS)
The data path of a
typical Von
Neumann machine.
Tanenbaum, Structured Computer
Organization, Fifth Edition, (c) 2006
Pearson Education, Inc. All rights
reserved. 0-13-148521-0
1.
Register-to-register
2.
Register-to-memory (or mem-to-reg)
What’s missing?
1.
2.
3.
4.
5.
6.
7.
Fetch next instruction from memory into
instruction register.
Change program counter to point to next
instruction.
Determine type of instruction just fetched.
If instructions uses word in memory, determine
where it is.
If needed, fetch word from memory into CPU
register.
Execute the instruction.
Tanenbaum, Structured Computer
Organization, Fifth Edition, (c) 2006
Go to step 1 (to begin
executing
Pearson Education,
Inc. All rights next instruction).
reserved. 0-13-148521-0
1.
2.
3.
4.
5.
6.
7.
Fetch next instruction from memory into
instruction register.
Change program counter to point to next
instruction.
Determine type of instruction just fetched.
If instructions uses word in memory, determine
where it is.
If needed, fetch word from memory into CPU
Very similar to the JVM (see
register.
http://java.sun.com/docs/books/jvms/second_edition/html/Overview.d
oc.html#7143).
Execute the instruction.
Tanenbaum, Structured Computer
Organization, Fifth Edition, (c) 2006
Go to step 1 (to begin
executing
Pearson Education,
Inc. All rights next instruction).
reserved. 0-13-148521-0

A program that fetches, examines, and executes
the instructions of another program.
1.
Interpreted
2.
Compiled to bytecode
3.
Compiled to executable
1.
Interpreted
–
2.
need additional program (interpreter) to run
Compiled to bytecode
need additional program to compile to bytecode
– need additional program (interpreter) to run
bytecode
–
3.
Compiled to executable
–
–
need additional program (compiler) to create
executable
nothing required to run

First, recall CPU components:



CU
ALU
registers = small amount of high speed memory
 stores temp results and control info
 holds (only) one number
 PC = program counter
 points to next instruction to be executed
 PS = processor status (EFLAGS)

We’ll need a PC, a PS, and one other register,
the AC.
Where’s the PS?
...
An interpreter for aTanenbaum,
simple
computer
(written in Java).
Structured
Computer
Organization, Fifth Edition, (c) 2006
Pearson Education, Inc. All rights
reserved. 0-13-148521-0
An interpreter for aTanenbaum,
simple
computer
(written in Java).
Structured
Computer
Organization, Fifth Edition, (c) 2006
Pearson Education, Inc. All rights
reserved. 0-13-148521-0
1.
Specify microinstructions
2.
Specify machine language
3.
Implement in software, hardware, or hybrid


Late 50’s and on…
IBM (dominant company) defines a family or
“architecture”


Top end machines ($$$) execute all instructions in
hardware.
Bottom end machines ($) interpret many instructions
(and therefore run slowly)

Benefits
1.
2.
3.


Bugs (in instructions) can later be fixed.
One may add new instructions.
Supports development, testing, and documentation.
Big trend in 70s and 80s was towards CISC
(complex instruction set computer) with
hundreds of instructions.
(Author’s view of DEC is not “complete.” DEC
saw the advantages of RISC and introduced the
DEC Alpha processor which was much faster and
more powerful than Intel processors.)


70s – CISC simplified compiler design by
closing the gap between HLL and architecture.
RISC = reduced instruction set computer

1980 – Patterson et al. @ Berkeley - SPARC
 No interpreter – just hardware

1981 – Hennessy – MIPS




Initial emphasis on quick instruction execution
Issuing (starting the execution of) many
instructions in parallel is the key to good
performance.
Small number of instructions (~50) compared
with 200-300 for CISC.
4 or 5 RISC instruction = 1 CISC instructions


But RISC can be 10x faster!
Evolution of compiler technology made this
possible.

So why hasn’t RISC beat Intel (CISC)?



Market momentum
Economy of scale
486 had a RISC core (for frequently executed
instructions) w/ other instructions interpreted