Transcript Parallel optics at IMEC

Reasons for parallel optical
interconnects
Roel Baets
Ghent University - IMEC
Department of Information Technology (INTEC)
© intec 2000
Overview
• Introduction
• Electrical interconnects: the limitations
• Optical interconnects: the merits
• Optical interconnects: the challenges
• Conclusion
Date workshop, February 2004
http://www.intec.ugent.be/IO
Interconnect: what ?
Interconnects = transmission of information
Date workshop, February 2004
http://www.intec.ugent.be/IO
Optical interconnects
Optical interconnects is a success for
telecommunication

long-distance (several km)

shorter distance (tens to hundreds meters):

data-communications (LAN)

system-level interconnects
(parallel optical datalinks)
And shorter distance is electrical ?
Date workshop, February 2004
http://www.intec.ugent.be/IO
Electrical connections (1)
Electrical tracks on PCB exhibit high loss
1m 8mil 50 stripguide with GETEK dielectric
Solution

pre-emphasis driver = higher-power dissipation

repeaters = higher power dissipation + more real estate
Date workshop, February 2004
http://www.intec.ugent.be/IO
Electrical interconnects (2)
Electrical connectors are large
= a density problem
Electrical connector at best 2 Gbps/mm2
Date workshop, February 2004
http://www.intec.ugent.be/IO
Progress electrical interconnects
ITRS Roadmap 2003:

chip-to board for peripheral busses is 5 to 6
Gbps for differential pairs in 2008-2009

but limited to a small number of pins
Date workshop, February 2004
http://www.intec.ugent.be/IO
Optical interconnects !
Shorter-distance interconnects benefit from
optical technologies !
A good reason for optical interconnects:
optics is better than electrical interconnects
in terms of

power dissipation is distance independent

data density: Gbps per mm2 is larger

transmission distance: loss in fibre is negligible
and data rate independent
Date workshop, February 2004
http://www.intec.ugent.be/IO
Parallel optics: merits
Reduced power dissipation, especially for long-distance

Typical power dissipation per link, for 2.5 Gbps, is 20-30mW
Larger data density due to 2-D parallelism !

Electrical backplane connector is limited to 50 Gbps/cm

Optical backplane connector allows >50 Gbps/mm2 , thus few
Tbps/cm
1000000
maximal
bandwidth
over 60cm
backpanel
[Gbps]
100000
10000
1000
100
optical upper limit
Assuming 250um pitch
(smaller pitch is possible)
Date workshop, February 2004
optical - IO
connectors
electrical upper limit
B=B0A/L2
(D.A.B. Miller)
electrical state-ofthe-art
ATCA backpanel
extrapolated to
12.5Gbps line rate
http://www.intec.ugent.be/IO
Parallel optics: merits
Longer transmission distances

optical loss is <1dB/m, loss electrical track on backplane is
>5dB (1m @ 2.5Gbps)
Smaller chip size

opto driver and receiver circuit is comparable to (or even
smaller than) LVDS circuit (for given technology)
Simpler system design !!

optical path replaces high-speed electrical tracks, thus simpler
packaging and PCBs

optics is scalable: same transceiver for intra-board, board-toboard AND system-to-system interconnects !
Date workshop, February 2004
http://www.intec.ugent.be/IO
Optical interconnects ?
So why is optics not yet inside your
computer today ?

Optics is a new technology (30 years younger
than electronics), components are available only
recently

Optics integration requires different novel
technologies, optics seems complex

Performance of electrical interconnects is
acceptable for current applications
Date workshop, February 2004
http://www.intec.ugent.be/IO
Optics: where and when ?
According to different roadmaps, optical
interconnects will be introduced in system
around 2008:
Electrical
Source: INTEL (2002)
Date workshop, February 2004
http://www.intec.ugent.be/IO
Interfacing optics to CMOS
Optical interconnect needs

ED: digital CMOS circuitry

EA: analog driver + receiver circuitry

OE: light sources (or modulators) and detectors

O: passive optical pathway (fiber, waveguides in
board, free space)
Options:


EA+OE+interface to O in one package
in some applications: ED+EA+OE+O in one
package
Date workshop, February 2004
http://www.intec.ugent.be/IO
Building OE on electronic ICs
Key challenges:
• integration of OE components on EA chips

yield

cost
• packaging of this chip to allow for
interfacing to optical pathway

alignment issues

hermeticity issues

thermal issues
• integration of optical interconnect into the
IC design methodology
Date workshop, February 2004
http://www.intec.ugent.be/IO
On-chip optical access: roadmap
Feasible with
future IC
technologies
Line-rate(over
CMOS
technology backpanel !!!)
65nm
90nm
0.13um
Fine-pitch
optics
12.5Gbps
10Gbps
5Gbps
3.125Gbps
0.18um
2.5Gbps
0.35um
1.25Gbps
8
16
32
64
128
256
512
Date workshop, February 2004
2x16x16
4x8x8
16x16
2x8x8
8x8
4x8
2x8
4x4
1x8
Feasible today
#channels
Degree of
parallelism
http://www.intec.ugent.be/IO
Conclusions
The road ahead
Bridge the 30-years age gap with electrical
interconnects

(extra) proof of reliability
Offer an integrated solution

Bring all components vendors together

Optimise performance of components to get an
efficient and cost-effective link
Cooperate with the end-user
Date workshop, February 2004
http://www.intec.ugent.be/IO