Transcript Unit1: Modeling & Simulation Module3: Structural

Unit1: Modeling & Simulation
Module3: Structural Modeling
Topic: Interconnects Modeling
Introduction
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Interconnects are pieces of conducting wires deposited
on insulators.
Interconnects are those that connect different gates in
the circuit.
Interconnects have to be modeled in terms of R, L, C
They result in delay of the signals during their transient
analysis.
Modeling of interconnects
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Indicate delay as delay units on each interconnect.
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For more accurate evaluations, model the delay line by
an equivalent resistors and capacitors
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Reasonably good for small interconnects and medium
frequencies
Contd…
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For long interconnects, it must be broken into smaller
pieces and modeled as:
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Reasonably good for longer interconnects
Contd …
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Interconnect is essentially a distributed element similar
to transmission line.
Models will be as shown at fairly high frequencies.
 With these models one can simulate the voltage/current
– time characteristics or transient behavior of the
circuit.
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Tri-state logic
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One may use switches to disconnect sources to a
common interconnect bus.
Information about whether the source is connected or
not should also be given.
To provide information, a new state called high
impedance state or tri-state is used.
It is basically to resolve multiple driver problem.
Contd …
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With tri-state the third possible condition is high
impedance state.
Only one is enabled and can go high or low.
Contd …
Tri-state circuit has extra input called Enable (E).
 If enable  1, normal functioning of the circuit
 0, the outputs are completely disconnected
from the rest of the circuit.
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Input
Output
A
B
C
0
0
Z
0
1
0
1
1
1
1
(E)
(E)
Wired Logic
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So far described modeling techniques rely on two
assumptions:
◦ The information is processed by components and transmitted by
signals
◦ The information direction is unidirectional
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These assumptions are not generally valid.
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Possible to directly connect several outputs such that
the connecting net introduces new logic function known
as wired logic.
Wired-AND logic
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Both the outputs should be ‘1’ to get a ‘1’ on the bus
Wired-OR logic
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If one of the output is ‘1’, it is enough to get a ‘1’ on the
bus
Wired logic contd…
Simple model is to introduce a dummy gate
 Make ‘A’ and ‘B’ as special fan-outs of ‘C’ for correct
modeling
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For every wired signal X we should maintain two values:
◦ The driven value,
◦ The forced value,.