Transcript vdhulipala_tr_presentation

SoC Interconnect Modeling
Venkata Krishna N. Dhulipala
11/20/2008
Relevance and Motivation
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Most embedded systems today are built using
SoC (System on Chip) technology
As technology advances delay of transistors
and local interconnects scales down
augmenting clock rates
Since chip area is projected to increase,
length of global interconnects increases and
therefore their delay
Interconnect Modeling
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Resistance: R = (ρ/t ). (l/w),
ρ=resistivity is constant for given metal
w
l
t
h
s
Interconnect Modeling
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Capacitance:
C = (εox/h) . wl
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Coupling capacitance with adjacent wires
ignored here – Gives rise to crosstalk
Putting resistance and capacitance together
 Delay, Τpd = RC
A more detailed capacitance model is
discussed in the report
Interconnect Modeling
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Inductance: Significant at higher
frequencies, since impedance Z=R+jwL
Introduces second order effects like,
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(a) Over/under-shoot edges,
(b) L di/dt voltage drop,
(c) Long range crosstalk, and
(d) f-dependent R
Improve Timing
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Add signal Repeaters
Effectively partition On and Off-chip
interconnects
Space and ground shielding to eliminate
crosstalk
Report shows mathematical derivations
to minimize delay by addition of
repeaters and partitioning
Current and Future Work
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Current Tools – Mantle by Magma (place and
route), Primtime/Primetime-SI by Synopsys
(timing and signal integrity analysis), Allegro
by Cadence (chip-to-board interconnect
modeling)
Future & Research
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Parallel Repeater-Insertion – To account for
inductance effects
Interconnect delay aware RTL bus architectures
Noise-rejection interconnect design