Transcript ECE 561 Computer Systems

ECE 456 Computer Architecture
Lecture #11 – CPU (I)
Instructor: Honggang Wang
Fall 2013
Administrative Issues
• Homework #2
– Due Today, November 13
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A Computer System (Agenda)
Computer history (L#1)
Computer architecture = von Neumann architecture + interrupts (L#2)
Central
Processing
Unit
Memory
L#4 ~ 8
Interconnection Bus
L#11 ~
Input
/Output
L#9, 10
L#3
Parallel organizations: SMP, Clusters, NUMA, Vector/Array Processors
If time allows
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Topics
• CPU organization (Ch. 12.1)
• Register organization (Ch. 12.2)
• The arithmetic and logic unit (ALU, Ch 9)
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CPU Organization
Internal Memory of CPU
• CPU must:
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–
–
Fetch instructions
Interpret instructions
Fetch data
Process data
Write data
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CPU Internal Structure
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Register Organization
Memory Hierarchy
CPU
REGISTERS
C
A
C
H
E
MAIN
MEMORY
VIRTUAL
MEMORY
I/O
STORAGE
DEVICES
RAID
Internal
Memory
OS level
Not real
External
Memory
• Registers
– Temporary storage inside the CPU
– Number and function vary between processor designs
– Top level of memory hierarchy
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Registers
• User-visible registers
– visible to machine/assembly language programmer
– optimizing use can minimize main memory references
• Control and status registers
– used by control unit to control operation of the CPU
– used by OS to control the execution of programs
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User-Visible Registers
• May be true general purpose (GPR)
• May be restricted for stack or floating-point
• May be used for data or addressing
– Data registers
• used only to hold data
• example: accumulator (AC)
– Address registers
• devote to the calculation of addresses
• example: segment registers, stack pointer
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User-Visible Registers (Cont’d)
• May be used for condition codes (flags)
– individual bit set by CPU
– indicates the result of an operation (zero, positive,…)
– Can be read (implicitly) by programs
• e.g. jump if zero
– Can not (usually) be set/altered by programmers
– Condition code bits are collected into condition code
registers
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Design Issues (1)
• Whether to use completely general-purpose
registers or to specialize their use
– make them general purpose
• increase flexibility and programmer options
• increase instruction size & complexity
– make them specialized
• smaller (faster) instructions
• less flexibility
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Design Issues (2)
• How many registers?
– Fewer = more memory references
– More does not noticeably reduce memory references and
takes up processor real estate
– Optimum: between 8 - 32
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Design Issues (3)
• How big?
– Large enough to hold full addresses
– Large enough to hold full words
– Often possible to combine two data registers
• double length integer
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Control & Status Registers (1)
• Program counter (PC)
– contains the address of the next instruction to be fetched
• Instruction register (IR)
– contains the instruction being executed
• Memory buffer register (MBR)
– contains a word to be stored in memory or receives a word from
memory
• Memory address register (MAR)
– specifies the memory address for the word to be written from
MBR or read into MBR
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Control & Status Registers (2)
• Program status word (PSW)
– sign, zero, carry, equal, overflow, interrupt
enable/disable, supervisor
• May have other registers pointing to:
– interrupt vectors used with vectored interrupt
– page table used with virtual memory
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Example Register Organizations (1)
• 18 32-bit registers
– 8 data registers:
allowing 8/16/32-bit
data operations
– 9 address registers
– Program counter
• A 16-bit status register
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Example Register Organizations (2)
• 16-bit registers
– 4 data registers:
allowing 8/16-bit data
operations
– 4 pointer registers
– 4 segment registers
– An instruction pointer
– 1 flag register
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Agenda
• CPU organization
• Register organization
– User-visible registers
– Control & status registers
– Examples
• The arithmetic and logic unit (ALU, Ch. 9)
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Arithmetic & Logic Unit (ALU)
• Performs arithmetic and logic operations on data
– Integer
– Floating point (real)
• Everything else in the computer is there to service
this unit
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ALU Topics
• Integer representation (Ch 9.2)
• Floating-point representation (Ch 9.4)
• Study yourself
– Computer arithmetic: negation, addition, subtraction,
multiplication, division
• Integer arithmetic (Ch 9.3)
• Floating-point arithmetic (Ch 9.5)
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ALU - Integer Representation
• Examples:
– 10012 = 910
- 01012 = - 510
101.012 = 5.2510
• Computers:
– No minus signs or period (radix points)
– Only have 0 & 1 to represent everything
– Treat the MSB as a sign bit
• 0: positive, 1: negative
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Integer Representation
• Sign-magnitude representations
• Twos complement representations
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Sign-Magnitude Representation (I)
• For an n-bit data word:
– the MSB is the sign bit
– the rightmost n-1 bits hold the magnitude of the integer
– e.g. +18 = 00010010
-18 = 10010010
– range:
 (2 n 1  1)  A  2 n 1  1
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Sign-Magnitude Representation (II)
• Drawbacks
– need to consider both sign and magnitude in
arithmetic
– two representations of zero (+0 and -0)
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Integer Representation
• Sign-magnitude representations
• Twos complement representations
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Two’s Compliment Representation (1)
• Positive numbers: same as for sign-magnitude
– +3 = 00000011
– +2 = 00000010
– +1 = 00000001
• Single ZERO:
– +0 = 00000000
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Two’s Compliment Representation (2)
• Negative numbers: take Boolean complement of each bit
of corresponding positive number, then add 1 to the
resulting bit pattern viewed as an unsigned integer
• Finding the two’s complement representation
of a negative number
– Step 1: form the binary representation of the corresponding
positive number
– Step 2: form complement: (reverse 1s to 0s and 0s to 1s)
– Step 3: add 1
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Example
• So for –1:
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–
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1:
00000001
Complement: 11111110
Add 1:
+1
Result:
11111111
Two’s Compliment Representation (3)
• Minimum negative number:
– 10000000 = -27
Range:
 2 n 1  A  2 n 1  1
Benefits: one representation of zero; arithmetic works easily
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Examples: 2’s Complement Addition
•
9:
+10:
-----19
•
9:
-10:
------1:
Note: In binary addition 1 + 0 = 1, 1 + 1 = 0 with a carry over of 1
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Conversion Between Different Bit Lengths
• Sign-magnitude representation:
– move the sign bit to the new MSB position & fill in
with 0s
– example:
4-bit  8-bit
• +3: 0011  00000011
• -3: 1011  10000011
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Conversion Between Different Bit Lengths
• 2’s complement representation:
– move the sign bit to the new MSB position & fill in
with sign bits
– example:
4-bit  8-bit
• +3: 0011  00000011
• -3: 1101  11111101
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ALU Topics
• Integer representation (Ch 9.2)
• Floating-point representation (Ch 9.4)
• Study yourself
– Computer arithmetic: negation, addition, subtraction,
multiplication, division
• Integer arithmetic (Ch 9.3)
• Floating-point arithmetic (Ch 9.5)
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Real Numbers
• Numbers with fractions
– 1001.1010 2 = 23 + 20 +2-1 + 2-3 =9.62510
• Where is the binary point?
– Fixed-point
• using integer representation
• very limited for very large numbers & very small fractions
– Floating-point
• using scientific notation for binary numbers
• allowing very large & very small numbers to be represented
with only a few digits
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Floating Point Representation
• +/- significand x 2exponent
• +/- (S): sign bit of significand (0/1)
• Exponent (k-bit)
– indicates binary point position
– uses biased representation: the true exponent value is obtained by
subtracting a bias (a fixed value: 2k-1 –1) from the biased exponent
• Base 2 is implicit
• Normalization: +/-1.bbbb…b x 2exponent
– MSB of significand is non-ZERO (1)
– Radix point is to the right of MSB of significand
– Both are implicit
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Floating Point (FP) Examples
implicit
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+ a bias of (27-1=127)
Hands-On Problems
• Consider a floating-point format with 8 bits for the biased
exponent and 23 bits for the significand and 1 bit for the
sign. Show the binary bit pattern for the following numbers
in this format.
1. Express the number in binary form
a) – 7
2. Normalize the number
b) 0.25
3. Find the biased exponent
4. Sign bit of the significand
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FP Ranges
• For a 32 bit number
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8 bit exponent
Negative numbers: [(2  223 )  2128 ,2127 ]
Positive numbers: [2127 , (2  223 )  2128 ]
Much larger than the range using 2s complement fixedpoint representation
[ 231 ,231  1]
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IEEE Standard 754
• Standard for floating point storage
• 32-bit single format with 8-bit exponent
• 64 bit double format with 11-bit exponent
• Extended formats (both mantissa and exponent) for
intermediate results
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Review Questions
1.
Explain how to determine if a number is negative in the
following representations
a) Sign-magnitude
b) 2s complement
c) Biased
2.
How can you form the negation of an integer in 2s
complement representation?
3.
What are the four essential elements of a number in
floating-point notation?
4.
What would be the bias value for a base-2 exponent in a
6-bit field?
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Solution
1.
Explain how to determine if a number is negative in the
following representations
a) Sign-magnitude
b) 2s complement
c) Biased
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•
In a) and b) the left-most bit is a sign bit, if the sign bit is 1,
the number is negative.
In c), a number is negative if the value of the representation
is less than the bias (2k-1-1)
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Solution
2.
•
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How can you form the negation of an integer in 2s
complement representation?
Take the Boolean complement of each bit of
corresponding positive number, then add 1 to the
resulting bit pattern viewed as an unsigned integer
Solution
3.
•
•
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What are the four essential elements of a number in
floating-point notation?
Sign, significand, exponent, base
+/- significand x 2exponent
Solution
4.
What would be the bias value for a base-2 exponent in a
6-bit field?
•
2k-1-1=31, where k=6
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Summary of Lecture #11
• CPU organization
• Register organization
– User-visible registers
– Control & status registers
– Examples: MC68000, Intel 8086, 80386 +
• The arithmetic and logic unit (ALU)
– Integer representation: sign-magnitude & 2s complement
– Floating point representation: normalization, biased-exponent
representation, IEEE 754
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Things To Do
• Continue to work on the project
• Read Ch 12.2, 12.5, 12.6 about register organization and examples
• Read Ch 9.3, 9.5 about computer arithmetic
• Check out the class website about
– lecture notes
– reading assignments
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Solution
5.
•
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Express the number EBA.C16 in IEEE Standard 754
format for 32-bit floating-point numbers
IEEE 754: 8 bits for the biased exponent and 23 bits for
the significand and 1 bit for the sign.
Solution to EBA.C16
1. Express the number in binary form: EBA.C16 = 111010111010.1100
2. Normalize the number into the form: +/- 1.bbbbbbbbbbb x 2exponent
1.110101110101100 x 21011
Once in a normalized form, every number has a 1 before the binary point. The
MSB of the significand, the base 2, the binary point are all implicit and are
not needed to store. So, in the significand field we will store
11010111010110000000000 (23 bits)
3.For the 8-bit biased exponent field, a bias of 127 is used. Add this bias to the
actual exponent and store the answer into exponent field: 10001010
4.sign bit = 0
5. Result: 0 10001010 11010111010110000000000
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Examples: 2’s Complement Addition
•
•
9:
+10:
-----19
9:
-10:
------1:
00001001
00001010
00010011
00001001
11110110
11111111
Note: In binary addition 1 + 0 = 1, 1 + 1 = 0 with a carry over of 1
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Solution to Hands-on Problems
1. Express the number in binary form: -7 = -111
2. Normalize the number into the form: +/- 1.bbbbbbbbbbb x 2exponent
-1.11 x 210
Once in a normalized form, every number has a 1 before the binary point. The
MSB of the significand, the base 2, the binary point are all implicit and are not
needed to store. So, in the significand field we will store
11000000000000000000000 (23 bits)
3.For the 8-bit biased exponent field, a bias of 127 is used. Add this bias to the
actual exponent and store the answer into exponent field: 10000001
4.sign bit = 1
5. Result: 1 10000001 11000000000000000000000
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Solution to Hands-on Problems
1. Express the number in binary form: 0.25 = 0.01000
2. Normalize the number into the form: +/- 1.bbbbbbbbbbb x 2exponent
1.000 x 2-10
In the significand field we will store 00000000000000000000000 (23 bits)
3.For the 8-bit biased exponent field, a bias of 127 is used. Add this bias
to the actual exponent and store the answer into exponent field:
01111101
4.sign bit = 0
5. Result: 0 01111101 00000000000000000000000
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Example Register Organizations (3)
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