Transcript Chapter 9 &10 - UWC Computer Science

William Stallings
Computer Organization
and Architecture
8th Edition
Chapter 9
Computer Arithmetic
Arithmetic & Logic Unit
• Does the calculations
• Everything else in the computer is there
to service this unit
• Handles integers
• May handle floating point (real) numbers
• May be separate FPU (maths coprocessor)
• May be on chip separate FPU (486DX +)
ALU Inputs and Outputs
Integer Representation
• Only have 0 & 1 to represent everything
• Positive numbers stored in binary
—e.g. 41=001010012
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No minus sign
No period
Sign-Magnitude
Two’s compliment
Sign-Magnitude
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Left most bit is sign bit
0 means positive
1 means negative
+18 = 000100102
-18 = 100100102
Problems
—Need to consider both sign and magnitude in
arithmetic
—Two representations of zero (+0 and -0)
Two’s Compliment
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+3
+2
+1
+0
-1
-2
-3
=
=
=
=
=
=
=
000000112
000000102
000000012
000000002
111111112
111111102
111111012
Benefits
• One representation of zero
• Arithmetic works easily (see later)
• Negating is fairly easy
—3 = 000000112
—Boolean complement gives
—Add 1 to LSB
111111002
111111012
Geometric Depiction of Twos
Complement Integers
Negation Special Case 1
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0=
000000002
Bitwise not
111111112
Add 1 to LSB
+12
Result
1 000000002
Overflow is ignored, so:
-0=0
Negation Special Case 2
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-128 =
100000002
bitwise not
011111112
Add 1 to LSB
+12
Result
100000002
So:
-(-128) = -128 X
Monitor MSB (sign bit)
It should change during negation
Range of Numbers
• 8 bit 2s compliment
—+127
— -128
= 011111112 = 27 -1
= 100000002 = -27
• 16 bit 2s compliment
—+32767 = 011111111 111111112 = 215 - 1
— -32768 = 100000000 000000002 = -215
Conversion Between Lengths
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Positive number pack with leading zeros
+18 =
000100102
+18 = 00000000 000100102
Negative numbers pack with leading ones
-18 =
100100102
-18 = 11111111 100100102
i.e. pack with MSB (sign bit)
Addition and Subtraction
• Normal binary addition
• Monitor sign bit for overflow
• Take twos compliment of substahend and
add to minuend
—i.e. a - b = a + (-b)
• So we only need addition and complement
circuits
Overflow rule
If two numbers are added, and they are
both positive or both negative, then
overflow occurs if and only if the result
has the opposite sign.
Subtraction and overflow
Hardware for Addition and Subtraction
Multiplication
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Complex
Work out partial product for each digit
Take care with place value (column)
Add partial products
Multiplication Example
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1011 Multiplicand (11 dec)
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x 1101 Multiplier
(13 dec)
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1011 Partial products
•
0000
Note: if multiplier bit is 1 copy
• 1011
multiplicand (place value)
• 1011
otherwise zero
• 10001111 Product (143 dec)
• Note: need double length result
Unsigned Binary Multiplication
Execution of Example
M – multiplicand Q – multiplier
Multiplying negative numbers
Flowchart for Unsigned Binary
Multiplication
Multiplying Negative Numbers
• This does not work!
• Solution 1
—Convert to positive if required
—Multiply as above
—If signs were different, negate answer
• Solution 2
—Booth’s algorithm
Booth’s Algorithm
Example of Booth’s Algorithm
Why does Booth’s Algorithm work?
M X (000111102)
=
=
=
=
M
M
M
M
X
X
X
X
(24+23+22+21)
(16+8+4+2)
(30)
(25 - 21 )
M X (011110102)
= M X (26+25+24+23+21)
= M X (27 - 23 +22 - 21 )
Division
• More complex than multiplication
• Negative numbers are really bad!
• Based on long division
Division of Unsigned Binary Integers
00001101
Quotient
1011 10010011
1011
001110
Partial
1011
Remainders
001111
1011
100
Dividend
Divisor
Remainder
Flowchart for Unsigned Binary Division
Twos complement division
1. Load the divisor into the M register and the dividend into the
A,Q registers.
2. Shift A,Q left one position.
3. If M and A have the same signs, perform A-M else perform
A+M
4. The preceding operation is successful if the sign of A is the
same as before, after the operation,
* if the operation is successful or A = 0, then set Q0 = 1
* if the operation is unsuccessful and A is = not 0 then set Q0
= 0 and restore the previous value of A.
5. Repeat steps 2 through 4 as many times as there are bit
positions in Q.
6. The remainder is in A. If the signs of the divisor and dividend
is the same, then the quotient is Q, else it is the twos
complement of Q.
Twos Complement Division
Twos complement division
1. Load the divisor into the M register and the dividend into the
A,Q registers.
2. Shift A,Q left one position.
3. If M and A have the same signs, Perform A-M else perform
A+M
4. The preceding operation is successful if the sign of A is the
same as before, after the operation,
* if the operation is successful or A = 0, then set Q0 = 1
* if the operation is unsuccessful and A is = not 0 then set Q0
= 0 and restore the previous value of A.
5. Repeat steps 2 through 4 as many times as there are bit
positions in Q.
6. The remainder is in A. If the signs of the divisor and dividend
is the same, then the quotient is Q, else it is the twos
complement of Q.
Twos Complement Division
Is this correct?
D=QXV+R
where
D =7
D =7
V=3
V=-3


Q= 2
Q= -2
R=1
R=1
D =-7
D =-7
V=3
V=-3


Q=-2
Q= 2
R = -1
R = -1
Preferred way to do two’s complement is to
convert operand into unsigned values and
at the end to account for the signs.
Real Numbers
• Numbers with fractions
• Standard format or scientific notation
• Also referred to as a floating point number
3752.610
= 3.7526 x 103
0.3752610 = 3.7526 x 10-1
Real Binary Numbers
• Numbers with fractions
• Could be done in pure binary
—1001.10102 = 24 + 20 +2-1 + 2-3 =9.625
• Where is the binary point?
• Fixed?
—Very limited
• Moving?
—How do you show where it is?
Floating Point
• +/- .significand x 2exponent
• Misnomer
• Point is actually fixed between sign bit and body
of mantissa
• Exponent indicates place value (point position)
Floating Point Examples
Signs for Floating Point
• Mantissa (or significand) is stored in 2s
compliment
• Exponent is in excess or biased notation
—e.g. Excess (bias) 127 means
—For the 8 bit exponent field the value range 0255
—Add 127 to the true exponent to get value to
be stored
—Thus a range of -127 to +128 can be stored
Normalization
• FP numbers are usually normalized
• i.e. exponent is adjusted so that leading
bit (MSB) of mantissa is 1
• Since it is always 1 there is no need to
store it
• (c.f. Scientific notation where numbers
are normalized to give a single digit
before the decimal point
• e.g. 3.123 x 103)
Integer Ranges
For a 32 bit number using the twos
complement integer representation, all
the integers from
— - 231 to +(231 – 1) can be represented.
Floating Point Ranges
• For a 32 bit number
—8 bit exponent and
—24 bit significand
• The 8 bit exponent is in biased
representation thus 127 is added to move
the range from
(-127 to +128)
to
(0 to +255)
Expressible Numbers
Why the 2 - 2-23
• Let us assume we have a 3 bit significand
—The biggest number we can then represent is
1.1112
— thus
10.0002 – 0.0012
= 210 – 2-310
Density of Floating Point Numbers
Why?
Let us again assume we want to write
numbers between 0 and 2
— 0
2-3 2-2 2-1 20
21
0__ ⅛__ ¼__½__ 1__________2
IEEE 754 Formats
sign biased
bit exponent
IEEE 754
Formats
trailing
significand field
8 bits
23 bits
(a) binary32 format
sign
biased
bit
exponent
trailing significand field
11 bits
(b) binary64 format
52 bits
sign
bit
biased
exponent
15 bits
(c) binary128 format
trailing significand field
112 bits
Figure 10.21 IEEE 754 Formats
IEEE 754
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Standard for floating point storage
32, 64 and 128 bit standards
8, 11 and 15 bit exponent respectively
Extended formats (both mantissa and
exponent) for intermediate results
FP Arithmetic +/•
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Check for zeros
Align significands (adjusting exponents)
Add or subtract significands
Normalize result
Arithmetic examples
• X=0.3X102=30
• Y=0.2X103=200
• X+Y=(0.3X102-3+0.2)X103
=(0.3X10-1+0.2)X103
=(0.03+0.2)X103
=(0.23)X103
=230
Arithmetic examples
• X=0.3x102=30
• Y=0.2x103=200
• XxY=(0.3x0.2)x102+3
=(0.06)x105
=6000
FP Addition & Subtraction Flowchart
FP Arithmetic x/
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Check for zero
Add/subtract exponents
Multiply/divide significands (watch sign)
Normalize
Round
All intermediate results should be in
double length storage
Floating Point Multiplication
Floating Point Division
Required Reading
• Stallings Chapter 9
• IEEE 754 on IEEE Web site