Transcript Full Adder Display

Full Adder Display
Topics
•
•
•
•
A 1 bit adder with LED display
Ripple Adder
Signed/Unsigned Subtraction
Hardware Implementation of 4-bit
adder
Implementation of a Full Adder
(carry-in)
C = 𝑧 ⊕ (𝑥 ⊕ 𝑦)
𝑆 = 𝑧 𝑥 ⊕ 𝑦 + 𝑥𝑦
Verilog Implementation
Use switches to input binary
numbers—x, y, and z.
z is the carry-in.
Display the output on the LED.
Press a button to determine
which bit will be displayed.
s represents the sum bit.
c represents the carry-out bit.
A mux is used to determine
Whether s or c should be displayed.
Multiplexing 7-Segment Displays
(Last Week)
If s[1:0]=00, then x[3:0].
If s[1:0]=01, then x[7:4].
If s[1:0]=10, then x[11:8].
If s[1:0]=11, then x[15:12].
Use Quad 4-to-1 mux
Get values for an[3:0] from btn[3:0] so that only one LED is displayed.
Explanation of the Code
If btn[0] is pushed, t[0] is 0.
If btn[1] is pusehd, t[0] is 1.
So we can use t[0] as a selector bit
for the MUX.
t[ ] =s[]
If the output of the MUX is a 0, a 0
Is displayed.
If the output of the MUX is a 1, a 1 is displayed.
Implementation of a Full Adder
(carry-in)
C = 𝑧 ⊕ (𝑥 ⊕ 𝑦)
𝑆 = 𝑧 𝑥 ⊕ 𝑦 + 𝑥𝑦
Four-Bit Adder
C4 is calculated last because it takes C0 8 gates to reach C4
Each FA uses 2 XOR, 2 AND and 1 OR gate.
A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.
Alternative Naming Convention
for the Full Adder
Pi = (𝐴𝑖 ⊕ 𝐵𝑖)
𝐺𝑖 = 𝐴𝑖𝐵𝑖
Si = (𝑃𝑖 ⊕ 𝐶𝑖)
C𝑖 + 1 = 𝐺𝑖 + 𝑃𝑖𝐶𝑖
Hardware Simplification
C0 =input carry
C1 = 𝐺0 + 𝑃0𝐶0
C2 = 𝐺1 + 𝑃1𝐶1 = 𝐺1 + 𝑃1 𝐺0 + 𝑃0𝐶0 = 𝐺1 + 𝑃1𝐺0 + 𝑃1𝑃0𝐶0
𝐶3 = 𝐺2 + 𝑃2𝐶2 = 𝐺2 + 𝑃2 𝐺1 + 𝑃1𝐺0 + 𝑃1𝑃0𝐶0 = 𝐺2 +
𝑃2𝐺1 + 𝑃2𝑃1𝐺0 + 𝑃2𝑃1𝑃0𝐶0)
2 gate delays for C3!
Four-bit adder with Carry
Lookahead
Ripple adder uses 8 XOR, 8 AND and 4 OR gate.
Lookahead implementation: 8 XOR, (4+6) AND, 1 2-input
OR, 2 3-input OR.
Advantages
• C1, C2 and C3 do not have to wait for
C1 and C2 to progate.
• C3 is propagated at the same time as
C1 and C2.
carry_lookahead.v
four_bit_adder_carry_lookahead.v
four_adder_carry_lookahead_top.v
Topics
• Calculations Examples
– Signed Binary Number
– Unsigned Binary Number
• Hardware Implementation
• Overflow Condition
Unsigned Number
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
(2-bit example)
Unsigned Addition
• 1+2=
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
+
Decimal
b
1
b
0
1
0
1
2
1
0
3
1
1
Unsigned Addition
• 1+3=
(Indicates Overflow)
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
Decimal
b
1
b
0
1 1
+
1
0
1
3
1
1
4
1 0
0
(Carry Out)
Overflow can be an issue in unsigned addition.
Unsigned Subtraction (1)
• 1-2=
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
+
Decimal
b
1
b
0
1
0
1
-2
1
0
1
1
0
0
(1’s complement)
0
1
(2’s complement)
-1
Unsigned Subtraction (2)
• 2-1=
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
Decimal
b1 b0
1
+
2
1
0
-1
1
1
1 0
1
3
Discarded
Summary for Unsigned
Addition/Subtraction
• Overflow can be an issue in unsigned
addition
• Unsigned Subtraction (M-N)
– If M≥N, and end carry will be
produced. The end carry is discarded.
– If M<N,
• Take the 2’s complement of the sum
• Place a negative sign in front
Signed Binary Numbers
• 4-bit binary number
– 1 bit is used as a signed bit
– -8 to +7
– 2’s complement
Signed Addition (70+80)
b7
0
b6
b5
b4
b3
b2
b1
b0
1
70
0
1
0
0
0
1
1
0
80
0
1
0
1
0
0
0
0
1
0
0
1
0
1
1
0
(Indicates a negative number)
70=21+22+26=2+4+64
80=24+26=16+64
010010110
10010110→01101001 →01101010
21+23+25+26=2+8+32+64=106
10010110↔-106
010010110↔ 21+22+24+27=2+4+16+128=150
Conclusion: There is a problem of overflow
Fix: Use the end carry as the sign bit, and let b7 be
the extra bit.
Signed Subtraction (70-80)
b7
b6
b5
b4
b3
b2
b1
b0
70
0
1
0
0
0
1
1
0
-80
1
0
1
1
0
0
0
0
1
1
1
1
0
1
1
0
(Indicates a negative number)
70=21+22+26=2+4+64
(No Problem)
80=24+26=16+64=01010000→10101111→10110000
11110110→00001001 →00001010
21+23=10
11110110↔-10
Signed Subtraction (-70-80)
b7
b6
b5
0
1
1
-70
1
0
-80
1
0
1
b4
b3
b2
b1
b0
1
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
(Indicates a positive number! A negative number expected.)
70=21+22+26=2+4+64
80=24+26=16+64
101101010 →010010101 → 010010110
010010110 ↔21+22+24+27=2+4+16+128=150
101101010 ↔-150
Conclusion: There is a problem of overflow
Fix: Use the end carry as the sign bit, and let b7 be
the extra bit.
Observations
• Given the similarity between addition
and subtraction, same hardware can be
used.
• Overflow is an issue that needs to be
addressed in the hardware
implementation
• A signed number is not processed any
different from an unsigned number. The
programmer must interpret the results of
addition and subtraction appropriately.
Four-Bit Adder-Subtractor
The Mode Input (1)
If M=0, 𝐵0 ⊕ 0= 𝐵0
If M=1, 𝐵0 ⊕ 1= 𝐵0
B0⊕ 𝑀
The Mode Input (2)
If M=0, C0 = 0
If M=1, C0 = 1
M=0 (Addition)
B3
B2
B1
B0
0
M=1 (Subtraction)
𝐵3
𝐵2
𝐵1
𝐵0
1
2’s complement is generated of B is generated!
Unsigned Addition
When two unsigned numbers are added,
an overflow is detected from the end carry.
Detect Overflow in Signed
Addition
Observe
1. The cary into the sign bit
2. The carry out of the sign bit
If they are not equal,
they indicate an overflow.
FPGA Demo: 12+15
FPGA: 15-12
FPGA: 12-15