Subtractor/Multiplier

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Transcript Subtractor/Multiplier

Subtractor/Multiplier
Section 4.5 & 4.7
Outline
• Delay
• Four Bit Subtractor
• Multiplier
Four Bit Adder
Erroneous Results When Delay is
inserted in half_adder.v
Four-Bit Adder
C4 is calculated last because it takes C0 8 gates to reach C4
Each FA uses 2 XOR, 2 AND and 1 OR gate.
A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.
Build a Full-Adder Circuit
M1
M2
w1
w2
One gate-delay
w3
Wait for the four bit adder circuit
to compute the results
Verilog and Jobs
Job: Mixed signal design job in San Jose, CA
Level: BS/MS in EE
•
Job Description:
We are seeking a Mixed-Signal ASIC Verification Engineer. The successful candidate will be a key
member of the team developing custom ICs for display modules based on the QMT SMI display
technology. Hands on technical contributor in verification of Mixed-Signal ASICs and IP
development projects. A candidate will help architect, specify, and lead the implementation of
mixed Analog/Digital verification projects using high level verification languages. You will work very
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to implement complete verification environments and methodologies. Design Mixed-Mode
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automatic checker.
Responsibilities: Create re-usable AMS testbenches from grounds up using advanced verification
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verification. Develop and maintain behavioral models (VerilogA/VerilogAMS) of analog and mixedsignal blocks including data converters(ADC/DAC), power converters (charge pump, buck
converter, boost converter), switch mode power supplies, LDOs, analog switches/muxes, PLLs, levelshifters, amplifiers, thermal sensors.
Verilog and FPGA
Parker Aerospace, an operating segment of Parker Hannifin Corporation, is one of the world’s leading producers of flight control,
hydraulic, fuel, inerting, fluid conveyance, thermal management, and engine systems and components for the aerospace
industry. We design and build equipment for virtually every aircraft and aero engine being produced in the world today.
ENGINEER III – AIRCRAFT ELECTRONICS
SUMMARY
Responsible for design, verification and certification of FPGA based aerospace firmware. Requirements creation and validation,
conceptual design, detail design and testing. Create control circuits, design (writing of VHDL), develop timing constraints, simulate
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are correct and complete. Creation of verification requirements based test cases and oversight of verification simulations by
supplier. Verify test cases, procedures, and test benches are created to satisfy existing design requirements. Perform independent
audit of verification artifacts. Participate in peer design reviews and support continuous process improvements.
Bachelor’s Degree in Electrical Engineering or related engineering discipline with preferably six plus years of experience in the
design, development and certification of aerospace firmware. A Master’s Degree is a plus. Specific experience in DO-254
certification required. Specific experience in motor drive and flight control applications is a plus. Experience with ARINC-429, CAN,
SPI or other serial interfaces. Experience in requirements capture and validation. Experience with VHDL design and
verification. Experience with Xilinx and Altera development tools. Experience with ModelSim/QuestaSim to perform simulation and
debug of VHDL design. Experience with in-circuit verification techniques. Possess excellent trouble shooting skills and
knowledgeable in Chipscope / Signal Tap FGPA debugging tools. Experience creating requirements based test cases. Experience
creating simulation / verification test bench using VHDL / Verilog language. Experience in supporting FAA SOI audits. Leadership
experience a plus. Strong technical writing, verbal and written communication skills. Excellent work ethic. Able to work well in
teams (local as well as remote) and is self-motivated.
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Subtraction
Unsigned Number
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
(2-bit example)
Unsigned Addition
• 1+2=
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
+
Decimal
b1
b0
1
0
1
2
1
0
3
1
1
Unsigned Addition
• 1+3=
(Indicates Overflow)
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
Decimal
b
1
b
0
1 1
+
1
0
1
3
1
1
4
1 0
0
(Carry Out)
Overflow can be an issue in unsigned addition.
Unsigned Subtraction (1)
• 1-2=
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
+
Decimal
b
1
b
0
1
0
1
-2
1
0
1
1
0
0
(1’s complement)
0
1
(2’s complement)
-1
Unsigned Subtraction (2)
• 2-1=
Decimal
b1
b0
0
0
0
1
0
1
2
1
0
3
1
1
Decimal
b1 b0
1
+
2
1
0
-1
1
1
1 0
1
3
Discarded
Summary for Unsigned
Addition/Subtraction
• Overflow can be an issue in unsigned
addition (An overflow is detected from
the end carry out of the most significant
position)
• Unsigned Subtraction (M-N)
– If M≥N, and end carry will be
produced. The end carry is discarded.
– If M<N,
• Take the 2’s complement of the sum
• Place a negative sign in front
Four-Bit Adder-Subtractor
For detecting
overflow in unsigned
numbers
For detecting overflow in addition/subtraction of signed numbers
The Mode Input (1)
If M=0, 𝐵0 ⊕ 0= 𝐵0
If M=1, 𝐵0 ⊕ 1= 𝐵0
B0⊕ 𝑀
The Mode Input (2)
If M=0, C0 = 0
If M=1, C0 = 1
M=0 (Addition)
B3
B2
B1
B0
0
M=1 (Subtraction)
𝐵3
𝐵2
𝐵1
𝐵0
1
2’s complement is generated of B is generated!
Four-Bit Adder-Subtractor
X2
X3
X_FA_2
X_FA_3
FA3
X4
X_FA_1
FA2
X0
X1
X_FA_0
FA1
FA0
Verilog Model of a 4 bit
adder/subtractor
Sample output of
adder/subtractor circuit
Ignore V if you are working with unsigned numbers.
Binary Multiplication
Two-Bit Binary Multiplier
(multiplicand)
(multiplier)
𝐴0𝐵0
𝐴0
B0
𝐴0𝐵0
0
0
0
0
1
0
1
0
0
1
1
1
Use an AND gate to multiply A0 and B0
Hardware Correlation
Hardware Correlation
G1
G3
W3
HA1
G0
G2
W2
W1
W0
HA0