Transcript Where the detector currents return path - Indico

N.Bondar, A.Kachtchouk, P.Neustroev
(PNPI)
30 September 2005, Frascati
From CARDIAC version 2
to CARDIAC version 3
Anatoli Kachtchouk)
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Anatoli Kachtchouk)
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FC
(only for Idet.)
Anode Ampl.
2 Cathode pads
i(t)
f(10-300)MHz
Cathode Ampl.
GND Bus Bar
(only for Idigital)
The detector current returns along the foil of the outer panel (only!)
All cathodes are segmented in DCRO
30 September 2005, Frascati
Wire strip
Anatoli Kachtchouk)
Where the detector currents return path
in M3R1 (DCRO)?
4
5
Where the digital currents return path?
2 phases has to be considered:
1) Digital currents return through the lowest impedance provided by local blocking
capacitors located near chips on FEB;
2) Charge recovering process: same currents from VR through Vdd/GND Bus Bar
From VR
 I Digital
Vdd Bus Bar
To next FEB
ZW
ZW
FEB
Idet
Digital
R
Blocking Capacitors
on boards
ZW
FC
I FC
2 layers in DCRO (very pure)
6 layers in SCRO
10 layers in WPC
MP GND Bus Bar
I
Digital
Digital
Ampl
ZR4C
ZW
To Voltage Regulator (VR)
From
wire
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FEB
Idet
Ampl
To both
cathodes
Anatoli Kachtchouk)
e.g. two Front-End Boards (FEB) are shown for illustration
Log scale
Linear scale
TH scan hystogram (M3R2, Cathode, board 25P/A=3)
TH scan hystogram (M3R2, Cathode, board 25P/A=3)
8000
10000
7000
1000
Cathode pad, Cdet=100pF
5000
4000
Cathode pad (add 47uF to
Vdd)
3000
100pF
2000
Count in 1ms
Cathode pad, Cdet=100pF
Cathode pad (add 47uF to
Vdd)
100
100pF
10
1000
0
1
0
20
40
60
80
100
120
0
20
Threshold (reg.units)
40
60
80
Threshold (reg.units)
Threshold scan
100
120
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Count in 1ms
6000
Anatoli Kachtchouk)
6
7
EM pickup !
100pF+20cm
100pF+10cm
LVDS_termination
100000
10000
1000
100
10
1
30
40
50
60
70
80
90
100
110
Threshold scan
(96  74)  2.35mV 
TH  1kHz @
 2.5 fC   6.8 fC
12mV / fC 
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Log scale
100pF
Anatoli Kachtchouk)
M3R2
CARDIAC_neg.
M3R4 test
8
WPC#104
6000
5000
Cin=100pf
4000
Cin=200pf
3000
Anatoli Kachtchouk)
Cin=detector
2000
1000
0
40
50
60
70
80
90
100
Threshold (reg.units)
M3R4 test
Noise Count Rate per 1ms
10000
1000
Cin=100pf
100
Cin=200pf
Cin=detector
10
1
40
50
60
70
80
90
100
Threshold (reg.units)
TH  1kHz @
(84  69)  2.35mV 
 2.5 fC   6.4 fC
9mV / fC 
30 September 2005, Frascati
Noise C ount Rate per 1ms
7000
9
from v.2 to v.3
PWR connector (+2.5V/GND)
pin1
+/-
pin1
2x7=14pin
pin1-7 +2.5V
pin8-14 GND
62.99
2x8=16pin (with locks)
48.2
Top view
pin1
CTRL-out
2x5=10pin
CTRL-in
2x5=10pin
1.65
Input 16-9 (bottom)
1x17=17pin
49.53
A.Kashchuk
P.Ciambrone
20.02.04
4 pads to FC
R  4
between A and D GND
30 September 2005, Frascati
pin1
4 pads to FC
R  4
between A and D GND
Anatoli Kachtchouk)
Input 1-8 (bottom)
1x17=17pin
1.65
59.69
LVDS connector (no GND)
10
Proposed Ground and Vdd network
Inp
Ampl
A_GND
Discr.
R 4.3 Ohm
Dialog
D_GND
Input_stage_ground of CARIOCA chip (which is the detector GND, also
extended to the corners on board and to guard ground between input pins)
must be separated from other grounds and connected together close to the
LV connector (incoming/outgoing GND).
Install resistor 4.3 Ohm separating detector and digital GND (see slide 11),
then 4 corners can be connected to FC (preventing instability).
Blocking capacitors on VDD must be connected to the corresponding ground
(digital to digital etc.), eliminate mixture in connections.
30 September 2005, Frascati
CARIOCA
Anatoli Kachtchouk)
Vdd
CARIOCA
Iinp
Cin
Idet
Ampl
Discr.
Dialog
Cdet
A_GND
R 4.3 Ohm
Iinp = Inoise - Idet
The larger C det – the smaller I inp
Possible solution – Organize power plane 1 for Cardiac chip
and plane 2 for Dialog chip
- Split ground plane for 2 parts
D_GND
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Cpar
11
Anatoli Kachtchouk)
There is pick-up from I2C bus (any line) to CARIOCA inputs: must
be improved by extra measures
Suggestions:
12
Change LV connector to the previous type 14-pin (8 pins for ground,
6 for VDD) or another one to be incompatible to I2C connectors.
LVDS connector must be specified and installed on boards as a
connector with locks
Anatoli Kachtchouk)
CARIOCA polarity (2 jumpers on board) and Address (4 jumpers
on board) have to be standard 2-pin 2.54mm jumpers to be easy
reinstalled by hands.
Ground (pin 8) in the I2C bus in both connectors must be
disconnected from the ground on board, similar to LVDS.
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GRES remove (it is already blocked by 100nF through R=0)
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CARDIACv2.3. must be redesigned
There is pick-up from I2C bus (any line) to CARIOCA inputs: must be shielded
by ground layer
Input_stage_ground of CARIOCA chip (which is the detector GND, also
extended to the corners on board and to guard ground between input
pins) must be separated from other grounds and connected together
close to the LV connector (incoming/outgoing GND).
Install resistor 4.3 Ohm separating detector and digital GND (see slide 11), then
4 corners can be connected to FC (preventing instability).
Blocking capacitors on VDD must be connected to the corresponding ground
(digital to digital etc.), eliminate mixture in connections.
CARIOCA polarity (2 jumpers on board) and Address (4 jumpers on board)
have to be standard 2-pin 2.54mm jumpers to be easy reinstalled by
hands.
Change LV connector to the previous type 14-pin (8 pins for ground, 6 for VDD)
or another one to be incompatible to I2C connectors.
LVDS connector must be specified and installed on boards as a connector with
locks.
Ground (pin 8) in the I2C bus in both connectors must be disconnected from
the ground on board, similar to LVDS which have no ground.
Note: the same on SB.
GRES remove (it is already blocked by 100nF through R=0)
Remove personal names from pcb (this is at least collective property, e.g. my
as well)
There are also many other remarks:
e.g. increase gaps between Vdd and GND;
diameter of holes are extremely small, etc.

Servicing software must be rewritten
A special window for operation with MWPC only has to be created, to not mix
with many other tasks of SB.
It must be well defined, what to be there.
FE-channels have mistake in numbering (ch2 instead of ch1) according to
CERN definition
Thresholds must be separated at least for Wire and Cathode, and must be the
simplest way to correct some thresholds by direct and random
addressing via look_up_table of parameters.
The software must operate in register units to be not depended on
calibration…
The units mV, fC at present version are wrong.
Does not accept any rate window (only 1 and 10ms)
Must allow threshold scan at various rate windows for wires and cathodes.
All standard set of histogram characteristics has to be calculated
(entries, mean, rms, fit by Gaussian, etc.) at the end of the
threshold scan procedure and move to file
Note: FWHM of the Gaussian fit gives Cdet: important for diagnostics.
Q: Why so long time is spent for TH-scan: rate window 1-10ms x 224 channels
= 0.224-2.24 sec;
in reality 11 minutes independently at any rate window?
Q: What these messages mean ? I do not see anything bad in histo’s.
–
–
–
BAD CHANNEL node_id=60 i2c_ch=1 fe_addr=3 channel=3
BAD CHANNEL node_id=60 i2c_ch=1 fe_addr=3 channel=3
BAD CHANNEL node_id=60 i2c_ch=1 fe_addr=3 channel=3
Operator must decides ‘good or bad’
ALARM has to be specified and enabled by operator.
Change manipulations with Excel-files within program: rather stupid situation
at present - impossible use Excel in parallel.
It must be clear for understanding: thershold, width of pulse; delay of pulse,
logic, etc. (LUT gives this possibility: board by board)
Threshold must be scan once (at present each time), then only ‘set’ using LUT
in direct/random access, where only needed, if parameter is modified
The software must more clearly write/read and show the data to/from
DIALOG chip for information/modification, if operator decides do that.
SB does not recognize FEB address (right side) if no LV on the neighbor
branch (Left side). To localize only one FEB on one branch another
must have LV and missing I2C terminators
30 September 2005, Frascati

Anatoli Kachtchouk)
Impossible to set
different thresholds
for wire and cathode
(e.g. M3R2)
Provides
instability
in DCRO (e.g. M3R1)