Transcript Lecture 28

Lecture #28 PMOS
• LAST TIME: NMOS Electrical Model
– NMOS physical structure: W and L and dox,
• TODAY:
PMOS
– Physical structure
– CMOS
– Dynamic circuits (Ring oscillators)
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NMOS =device which carrier current using electrons but
on the surface of a p-type substrate (p-type substrate
means that no electrons are available)
N-MOS gate
source
drain
oxide insulator
n
In this device the gate controls
electron flow from source to drain.
(in the absence of gate voltage,
current is blocked)
n
P
VGS > Vt
-
+
gate
drain
source
oxide insulator
n
n
If we increase gate voltage
to a value greater than Vt
then a conducting channel
forms between source and
drain. (“Closed switch”)
P
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CMOS = Complementary MOS
(PMOS is a second Flavor)
source
N-MOS gate
drain
oxide insulator
n
n
P
In this device the gate controls
electron flow from source to drain.
It is made in p-type silicon.
The NEW FLAVOR! P-MOS
gate
In this device the gate controls hole
flow from source to drain.
It is made in n-type silicon. (In ntype silicon no positive charges
(“holes”) are normally around.)
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source
P-MOS
p
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drain
p
n-type Si
3
PMOS
gate
In this device the gate controls hole
flow from source to drain.
source
It is made in n-type silicon.
|VGS |>|Vt |
+
gate
drain
P-MOS
p
drain
p
n-type Si
What if we apply a big negative
voltage on the gate?
If |VGS |>|Vt | (both negative)
p
p
source
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n-type Si
then we induce a + charge on
the surface (holes)
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NMOS and PMOS Compared
NMOS
“Body”
– p-type
Source – n-type
Drain
– n-type
VGS
– positive
VT
– positive
VDS
– positive
ID
– positive (into drain)
G
S
D
ID
n
n
p
ID
B
ID
VGS=3V
1 mA
(for IDS =
1mA)
VGS= 3V
1 mA
(for IDS =
-1mA)
VGS=0
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PMOS
“Body”
– n-type
Source – p-type
Drain
– p-type
VGS
– negative
VT
– negative
VDS
– negative
ID
– negative (into drain)
G
S
D
ID
p
n
B
VGS=0
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2
3
4
DS
1
2
3
4
VDS
5
CIRCUIT SYMBOLS
D
G
D
G
S
NMOS circuit symbol
S
PMOS circuit symbol
A small circle is drawn at the gate
to remind us that the polarities are
reversed for PMOS.
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PMOS Transistor Switch Model
Operation compared to NMOS: It is complementary.
VDD
S
G
VDD
S
S
G
G
VDD
VG =0
VG = VDD
V=0
D
Switch OPEN
D
Switch CLOSED
D
For PMOS for the normal circuit connection is to connect
S to VDD (The function of the device is a “pull up”)
Switch is closed: Drain (D) is connected to Source (S) when VG =0
Switch is open :
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Drain (D) is disconnected from Source (S) when VG = VDD
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PMOS Model Refinement
PMOS transistor has an equivalent resistance RDP when closed
There is also a gate capacitance CGS, just as in NMOS
S
CG
S
G
P Ch
S
G
D
RDP
The circuit symbol
D
The Switch model
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CMOS
Challenge: build both NMOS and PMOS on a single silicon chip
NMOS needs a p-type substrate
PMOS needs an n-type substrate
Requires extra process steps
D
G
S
G
D
S
oxide
p
p
n-well
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n
n
P-Si
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THE BASIC STATIC CMOS INVERTER
For Vin > 1.5V NMOS on , PMOS off
VDD
VDD
source
PMOS
vin
drain
Vin
Vout
Vout = 0
vout
drain
NMOS
source
For Vin < 1V NMOS off , PMOS on
VDD
Example for Discussion:
NMOS: VTn = 1 V
Vin
Vout
Vout = VDD
PMOS: VTp = -1 V
Let VDD = 2.5V
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THE BASIC STATIC CMOS INVERTER
Quasi-static operation (ignoring transients)
For Vin > 2V NMOS on , PMOS off
VDD
VDD
source
PMOS
vin
drain
Vin
Vout
Vout = 0
vout
drain
NMOS
source
For Vin < 0.5V NMOS off , PMOS on
VDD
Example for Discussion:
NMOS: VTn = 0.5 V
Vin
Vout
Vout = VDD
PMOS: VTp = - 0.5 V
Let VDD = 2.5V
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CMOS INVERTER TRANSFER CURVE
VDD
Transfer Curve
2.5
PMOS
2
vin
NMOS
Vout
vout
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
Vin
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CHAIN OF CMOS INVERTERS
VDD
VDD
VDD
VDD
VDD
vin
VDD
Vout
STAGE M
Vin
Vout
If the input is toggled, the state of every inverter will change and there
will be a gate delay for every gate caused by the combination of the
output resistance of the switching devices combined with the input
capacitance of the following stage. Let’s estimate the stage delay.
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CHAIN OF CMOS INVERTERS STAGE-M
gate delay if input HIGH
“Open”
VDD
VDD
the model
VDD
VM
VM+1
VDD
CGP
VM
VM+1
RN
M
“Closed”
CGN
M+1
When the input VM is high, the lower (NMOS) switch is closed and according to
our model the resistor RN discharges the input capacitance of the next gate, the
capacitors CGN and CGP in parallel.
The time constant is RN(CGN+CGP) so the gate delay is 0.69 RN(CGN+CGP) .
We do not consider here the capacitance of the gates in Stage M, because they
load Stage M-1, and contribute to its delay.
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Core Circuit for “Pull-Down” Transition
CGp
Circuit only contains one
resistor and two
capacitors
Capacitors CGp and CGn
… how can they be
combined into one?
t=0
vout1 = v in2
+
-
VDD
D
Rn
CGn
V2= VDD
Capacitors share one node;
the other nodes are held at
constant voltages.
i(t)
vC(t)
KCL: currents sum at common
node, ie node capacitance is SUM
(parallel capacitor formula).
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C2
i2(t)
“Virtually
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lecture 28Parallel”
i1(t)
C1
V1= 0
Capacitors
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Pull-Down Equivalent Circuit
Two capacitors add for finding the charging current  applies to gate
capacitances
t = 0+
vout1
D
Precharge: VDD
CGn + CGp
Rn
VDD
Lets once more
associate circuit above
to the actual inverter
circuit.
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vout1 =
v in2
vin1
vout2
+
-
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Equivalent circuit vs actual circuit
t = 0+
vout1
D
Precharge: VDD
CGn + CGp
Rn
VDD
1) Remove inactive device
2) Replace load devices by
their input equivalents
3) Replace NMOS pulldown by by its output
equivalent.
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vout1
v in2
vin1
vout2
+
-
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Gate Delay from Pull-Down Equivalent Circuit
Capacitor is precharged to VDD and discharged to ground through
resistance Rn.
t = 0+
vout1
D
Precharge: VDD
CGn + CGp
Rn
We can compute the delay easily.
It is just an RC delay.
VDD
Vout1
VDD exp(-t/RC)
VDD
If we define the switching delay as the time
2
for the output voltage to swing halfway to its
new steady-state value, we will find the
switching delay is 0.69RC.
[remember
0.5 = exp(-0.69)]
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0.69
t/RC
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CHAIN OF CMOS INVERTERS STAGE-M
gate delay if input LOW
“CLOSED”
VDD
VDD
VDD
the model
VDD
VM
VM
VM+1
RP
CGP
VM+1
CGN
“Open”
M
M+1
When the input VM is low, the upper (PMOS) switch is closed and
according to our model the resistor RP charges the input capacitance of
the next gate, the capacitors CGN and CGP in parallel.
The time constant is RP(CGN+CGP) so the gate delay is 0.69 RP(CGN+CGP).
Normally we try to have equal rising and falling gate delay, so for the
simple inverter we design the transistors so RP = RN.
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CMOS PARAMETERS
3 generations of CMOS
Parameter
L (m)
IDS’ (A/[V-m])
V-1
VT V)
VDSAT V)
dOX nm)
CGS ‘fF/m2)
VDD V)
NMOS
(0.25m)
0.25
350
0.05
0.5
1
5
7
2.5
PMOS
(0.25m)
0.25
-175
0.05
- 0.5
-1
5
7
2.5
NMOS
(0.18m)
0.18
500
0.07
0.4
0.75
3.5
10
1.8
PMOS
(0.18m)
0.18
- 250
0.07
- 0.4
- 0.75
3.5
10
1.8
NMOS
(0.13m)
0.13
650
0.1
0.4
0.6
2.5
14
1.5
PMOS
(0.13m)
0.13
- 325
0.1
- 0.4
- 0.6
2.5
14
1.5
Return
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Interconnect layers
• On top of the transistor layers, many metal
layers interconnect the logic
Illustration
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Actual TEM photo
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CHAIN OF CMOS INVERTERS TO MEASURE tdelay
VDD
STAGE 1
STAGE 101
Vout
If the input is toggled, the state of every inverter will change and there will
be a gate delay for every gate. Suppose there are 1001 gates and we
move the input switch from VDD to ground. 1001 gate delays later the
output will go from ground to VDD.
But suppose in the meantime we moved the switch to connect to Vout (which
is initially zero).
At at time equal to exactly 1001 gate delays, the input to stage 1 will go
high, and after another equal time it will go low, etc. We have created a
“RING OSCILLATOR”, which toggles at a frequency equal to 1/(1001 tdelay ).
Such ring oscillators are commonly used to estimate the performance of a
technology. No switch is actually needed, the output is permanently wired to
the input, and the oscillations start when power is applied.
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CMOS INVERTERS DRIVING ANY LOAD
VDD
Vout
CLOAD
VDD
If we substitute the switch
model for the transistors we
have the following circuit:
No matter what the load is, the
behavior is the same: the
stage delay is 0.69RC where
C= CLOAD and R= RN if input is
switched high or R= RP if input
is switched low.
Rp
Rn
D
Vout
CLOAD
The actual load consists of whatever gates are attached to the node plus
any additional capacitance. In the next lecture we will compute the gate
capacitance on the input to any NAND logic block for example. As
another example, if an external wire is attached to a node with the wire
going to a printed circuit board, we will have a load of several pF.
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