Transcript Lecture #2 - Dr.Nazar Abbas Home Page

FPGA Based System Design
Lecture 2: Programming Technolgies
Dr. Nazar Abbas Saqib
NUST Institute of Information
Technology (NIIT)
[email protected]
We will discuss..
• Introduction to FPGAs
• Programming Technologies
Pl note the source of the figures included in this lecture:
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays
(FPGAs)
• FPGAs are digital integerated circuits (ICs) that contain
configurable (programmable) logic blocks of logic alongwith
configurable interconnects between thes blocks
•
The “field programmable” portion of the name refers that it can be
programmed “in the filed” and not hard wired. If a device is being
programmed while remaing resident in a system, it is termed as “In
System Programmable (ISP)
•
What distinguihes an FPGA from an ASIC is …something that
resides in its name “Field Programmable Gate Arrays”
We will discuss..
A boring circuit…
Logic 1
Potential links
a
Pull-up resistors
NOT
b
&
AND
NOT
y = 1 (N/A)
Fusible Link Technology
•
•
•
First technique that allowed users to program their devices
Devices come with all links in place-each link is referred to as fuse
Fuses can be selectively removed by applying pulses of high voltage and
current
Fuses
Logic 1
Fat
a
Pull-up resistors
Faf
NOT
Fbt
b
&
AND
Fbf
NOT
y = 0 (N/A)
Fusible Link Technology
Example: Programming for y= a & !b
Logic 1
Fat
a
Pull-up resistors
NOT
&
b
AND
Fbf
NOT
y = a & !b
AntiFuse Technology
•
•
•
Each configurable path has an associated link called as antifuse
In unprogrammed state, antifuse offer high resistence ‘open circuit’
Antifuses can be selectively grown by applying pulses of high voltage and
current
Unprogrammed
antifuses
a
Logic 1
Pull-up resistors
NOT
b
&
AND
NOT
y = 1 (N/A)
AntiFuse Technology
Example: Programming for y= !a & b
Programmed
antifuses
a
Logic 1
Pull-up resistors
NOT
b
&
AND
NOT
y = !a & b
AntiFuse Technology
Amorphous silicon column
Polysilicon via
Metal
Oxide
Metal
Substrate
(a) Before programming
(b) After programming
Growing an antifuse
Mask Programmed Devices
•
A single photomask is used to define which cells are to include a mask
programmed connection
Logic 1
Mask-programmed
connection
Pull-up resistor
Row
(word) line
Transistor
Logic 0
Column
(data) line
Fig: A transistor based mask
programmed ROM cell
PROM (Programmable ROM)
•
•
In its unprogrammed state, all fusible links are in place thus pulling down the
column line (data) to logic zero
Fuses can be selectively removed by applying pulses of high voltage and
current to place row line in active state, colum line (data) is pulled to logic 1
Logic 1
Fusible link
Pull-up resistor
Row
(word) line
Fig: A transistor and fusible link based
PROM cell
Transistor
Logic 0
Column
(data) line
EPROM (Eraseable Programmable
ROM) based Technologies
•
•
•
EPROM transistor is similar to standard MOS transistor with addition of a
floating gate
In its unprogrammed state, floating gate does not effect the operation of
control gate
To program, high voltage is supplied b/w gate and drain terminal that causes
the transistor on and also energetic electrons to flow through floating gate,
now even a progam signal is removed-a negative charge remains at floating
gate-it is enough stable and can be erased through ultravoilet reays
Source
terminal
Control gate
terminal
Drain
terminal
Source
terminal
Control gate
terminal
Drain
terminal
control gate
Silicon
dioxide
control gate
source
drain
(a) Standard MOS transistor
Silicon
substrate
floating gate
source
drain
(b) EPROM transistor
EPROM based Technology
Logic 1
Pull-up resistor
Row
(word) line
Fig: An EPROM transistor based memory cell
EPROM
Transistor
Logic 0
Column
(data) line
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
E2PROM based Technology
(Electrically Eraseable Programmable ROM)
•
•
An E2PROM cell is app 2.5 times larger than EPROM cell because it
comprises two transisitors and there is a space between them
An E2PROM cell is similar to EPROM cell in that it contains a floating gate.
The oxide layer b/w two transistors is very thin. The second transistor can be
used to erase the cell electrically
Normal
MOS transistor
E2PROM Cell
E2PROM
transistor
FLASH based Technology
•
Similar to EPROM and E2PROM cell but with thinner oxide layer & with
rapid erasure time
Normal
MOS transistor
E2PROM Cell
E2PROM
transistor
SRAM based Technology (Static RAM)
Two version of semiconductor RAM
DRAM (Dynamic RAM)
•
•
DRAM cell comprises a transistor resistor pair which ccupy less silicon
“Dynamic” because when capcitor loses charge, it requires to be
periodically recharged-cost of refreshing is too high
SRAM (Static RAM)
•
•
Static because once a value has been loaded into an SRAM cell, it
remains untill it get modified or power has been removed
Modern FPGAs are based on SRAM based technology
SRAM
Technology
Symbol
Predominantly
associated with ...
Fusible-link
SPLDs
Antifuse
FPGAs
EPROM
SPLDs and CPLDs
E2PROM/
FLASH
SPLDs and CPLDs
(some FPGAs)
SRAM
Figure 2-13
SRAM
FPGAs (some CPLDs)