Transcript CMP Modeling - University of Utah

Lecture 7.1
Device Physics – Transistor
Integrated Circuit
Base
Transistor
Collector

Bipolar Transistor
– Discrete device
– On Chip

Field Effect
Transistor (FET)
– On Chip
Emitter

Uses
 Amplify a signal
– Operational
Amplifier

Switch
– On/Off
• Process and store
binary data
Switch
Source
Closed
Gate
Reservoir
Water
Drain
Channel
Sink
Gate
Source
Open
Gate
Reservoir
Water
External
Energy
(voltage)
Drain
Gate
Sink
Bipolar Transistor

Combination of
two back-to-back
p-n junctions

P-N-P
 or
 N-P-N
Bipolar Transistor
Circuit Configurations
Single PN Junction
-Constant Gate Voltage
Base
Amplify Input Voltage Signal
Collector
Gain
Emitter
Amplifier Gain

Common-base configuration current
gain
– =1-(Wb/Lp)2/2 ~ 1 (slightly less than 1.0)
• Wb = width of base minus depletion regions
• Lp = diffusion length of holes in the base.

Voltage Gain
– ce= /(1- ) (values from 400 to 600)
FET- (Field Effect Transistor)

MOSFET
– Metal oxide
semiconductor
field effect
transistor


– Metal-insulatorsemiconductor FET

IGFET
NMOS or PMOS
MOST
– Metal-oxide
semiconductor
transistor
– Insulated-gate FET

MISFET

JFET
– Junction FET
MOSFET in Memory Chip
Source
Gate
Drain
Field Effect Transistor (FET)
Voltage Controlled Resistor
Inversion Zone - Poisson’s Eq.
 2U
= -/( o )
–Metal on
• N Zone
P Zone
n= - e Nd
-p=+ e Na
– Boundary Conditions
• U=Uo at x=0
• U=0 V at x=
Inversion Layer
Electron Tunneling

Electron Transmission, T, through
thickness, δ.
T  e 2
8 2me U  E 

h2

U=Potential Energy of Barrier
 E=Total Energy of Electron
Integrated Circuits

CPU or Memory
– First Layer
•
•
•
•
Transistors
Capacitors
Diode
Resistors
– Multi-layer
• Wiring
– Interconnects
– Bonding Pads
• Dielectric
• Capacitors
• Heterostructures
Transistor Switching Speed

PNP vs NPN
 N channel is Faster - NPN
– Mobility of n (electron is faster than hole)
Much Lower Switching Power

Complementary
MOS
– N channel
connected to P
channel
– 106 less power for
switching
• 1 pnp acts as
amplifier
• 2nd npn does the
switching
VT IS LESS for
Complementary Transistor
Integrated Circuit
Good for the next 20 years!

(Gordon E.) Moore’s
Law, 1965
– Doubling of transistor
density every year!
– Doubling of computer
speed in 18 months
– Doubling of computer
size in 18 months
– Substantial decrease
in price with time
By 2012
1 Billon Transistors/die
10 Ghz!
Limitations by 2017 (gate Thickness)
• Price of transistor is
10-6 of original price
http://developer.intel.com/update/archive/issue2/focus.htm
Size of Transistor
$1B/acre
5 layers of Metalization
Scaling Parameter = S >1

Linear Dimension L1L1/S
– Reduce all linear dimenstions by 1/S

Reduce voltage by 1/S
 Increase doping Concentrations by S
 Decrease time for electron to cross gate
– t = L1/Vdrift t/S, Vdrift= eE/me ,  =relaxation
time

Power Dissipated per transistor
– P = I V  (I/S)(V/S) P/S2
1 00
Circuit Speed
10
Computer Speed
t1( S)
1
1
GHz
t2( S)
0 .1
1
GHz
0 .0 1
1 1 0
3
1 1 0
4
1
10
1 00
1 1 0
3
S

Switching Time
– Time to take an
electron across a
gate
– t = L/Vdrift
• Vdrift= eE/me , 
=relaxation time
– t t/S

RC delay time of
Interconnects
– Resistance
• R=  L/A
• R=  L*S/A/S2  RS3
– Capacitance
• C=oA/d
• C =o(A/S2)/(d/S) 
C/S
– RC  RCS2
Copper Wiring/Low K dielectric

Pentium IV
– S < 0.18 μm
– Clocks @
>2.0 Ghz
What a Memory Chip Looks Like
DRAM memory Array
Memory
Chip
–First Layer
•Transistors
–Multi-layer
•Wiring
–Interconnects
–Bonding Pads
•Dielectric
•Capacitors
•Dielectric
Reading and Writing
Columns
Think of a memory chip as a grid
or array of capacitors located at
specific rows and columns. If
we choose to read the memory
cell located at row 3, column 5,
we will retrieve information from
a specific capacitor. Every time
we go to row 3, column 5, we
will access or address the same
capacitor and obtain the same
result (1) until the capacitive
charge is changed by a write
process.
Rows

1
2
3
4
5
6
7
1
1
0
0
1
0
1
1
2
0
0
1
1
1
0
1
3
0
1
1
0
1
1
0
4
1
1
0
0
0
1
1
5
1
0
41
0
0
1
0
6
1
1
1
0
1
0
0
7
0
1
0
1
1
0
1
DRAM Memory Cell
1 Bit
Column Line
Capacitor
Gate or
Row Line
READ
WRITE