Transcript display - EDGE - Rochester Institute of Technology

Automated TFT Noise
Characterization
Platform
Kendell Clark (EE), Stephen Marshall (EE),
Carmen Parisi (EE), James Spoth (CE), Ryan
Vaughan (ME)
Rochester Institute of Technology
Analog Devices Integrated Microsystems Laboratory
Agenda
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ADIML
Project Overview
Customer Needs
Specifications
Functionality so far
System Design
Schedule
Budget
Current Status
RIT
Project Overview
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ADIML
Noise Measurements of Thin-Film Devices on Glass is
necessary for understanding their operation and
modeling their behavior
Many noise measurements are required to accurately
model any new technology
1/f Noise measurements take a long time due to
extremely low frequencies (1 mHz)
Devices under test must be accurately biased for the
entire duration
RIT
Project Overview
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Design & build an automated low noise measurement
environment
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Computer-Controlled Low noise biasing
Low noise signal amplification
Interface with and unify operation of laboratory measurement apparatus
Lower budget than competing commercial solutions
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Cascade Microtech EDGE 1/f Noise Management System:
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$1.2 million, but has more functionality
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ADIML VIKING Platform
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Approximately $1,000
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ADIML
Thermal Chuck, Automated Probers, Automated Data Analysis, Higher Bandwidth, etc.
Aimed at commercial foundries improving process for marketing high-performance silicon
“Bare bones” automated noise measurements
Aimed at low budget research groups for characterization, rather than production testing
RIT
Customer Needs
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EMI/RFI Shielded Environment
Localized, low noise amplification of DUT noise signal
Low noise, programmable DC biasing of DUT
Immunity from 60Hz AC power interference
Full noise measurement cycle is software-controllable
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Interface with existing wafer probe station
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ADIML
IV Sweep  Device Bias  Noise Measurement  Data
Acquisition
Maintain full movement of wafer chuck and microscope gantry
Maintain view of wafer during measurement; RF shielding must remain
System must operate for several hours at a time
No clocks or oscillators inside shielded environment
RIT
Specifications
Spec Name
Overall System Gain Range
Amplifier BW
Contributed Noise at DUT Gate
Minimum Measureable Frequency
Input Referred Noise of LNA
Specification
(description)
Max system gain (adjustable)
Max system BW
Switches must not add significant
noise to the system, either
through 4kTR, or through contact
R modulation during
measurement.
Keep 1/f noise corners of system
components far enough below
this value to be able to measure
accurately at low frequencies
@ 10Hz
@ 10kHz
dB
Hz
Hz
Amplifier DC Bias Source Noise Performance
nV/rt(Hz)
Ground Isolation From Analog Circuitry
ADIML
Achieved
100k
180
1M
180
100k
1
20
3.2
1
10
1
100
20
500
50
32
25
500
300
50
3.2
0.001
s
0
V
V
A
A
Hours
-10
-10
EMI-shielded box for analog
circuitry (attenuation of ambient
noise)
BOOL
T
Analog GND must be quiet;
therefore must avoid ground
loops through isolation.
BOOL
T
Gate Bias Range
Amplifier DC Bias Range
Drain Current Resolution
Drain Current Range
Battery Life
RF Shielding
0.1
pA/rt(Hz)
pA/rt(Hz)
pA/rt(Hz)
Bias network settling time
(seperately, not in total)
40
10k
nV/rt(Hz)
Drain Current Source Noise Performance
Bias Settling Time
Max
Value
Unit of Measure Min Value Nominal Value
1n
3
0.5
10
10
10
2n
100u
[-10,10]
[-10,10]
5
RIT
Specifications - Problems
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Issue with current bias circuit prevents circuit from
settling.
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Drain bias current resolution not yet measurable:
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Nano- or pico-ammeter not available, still developing a
measurement circuit using LNA to amplify current
LNA has an offset voltage that affects results at high gain settings
Battery life untested.
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ADIML
Recent simulations show this can be fixed easily
9V batteries purchased could not output enough current for the
circuit
Need to purchase new batteries
RIT
Project Overview
PC
With LabVIEW
NI USB
Development
Board
Digital Control
Circuit
Biasing Circuit
ADIML
DUT
Signal
Conditioning
(Amplification)
Measurement
(DSA, B1500)
RIT
Analog Circuitry – Block
Diagram
ADIML
RIT
Analog Circuitry – Voltage Bias
Circuitry
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RCharge
Control
Voltage
RFilter
Charging
Relay
C
DUT
Gate or
LNA (-)
Terminal
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Control Voltage comes
from a DAC located on
the PCB.
RFilter & C form a LPF
with corner frequency
of 1mHz.
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LPF
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ADIML
RCharge allows for capacitor
to reach desired voltage
levels quickly.
>60dB attenuation of
noise in the
measurement frequency
range, 1Hz to 100kHz
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Resistor-Based Current Bias
Generation
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Uses battery and resistor,
or op-amp biasing scheme
to produce a fixed voltage
across a resistor
Fundamentally limited in
noise performance
 Resistor thermal noise
floor of RD
Image: Kwok K. Hung, et. Al. A Physics Based
MOSFET Noise Model for Circuit Simulators.
IEEE Trans. On Electron Devices. Vol. 37. May 1990.
ADIML
RIT
Analog Circuitry – Current Bias
Circuitry
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VDD
Sensitive
Measurement
DUT
Node
Control
Voltage
LPF
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Iout
C
LPF
Noise
Injection
ADIML
C
Rs
Uses a JFET-based current
source
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Permits isolation of resistors
from output current
Allows resistors to be filtered
without attenuating noise at
higher frequencies
Circuit topology offers
output impedance enhanced
by amplifier gain
RIT
Analog Circuitry – Current Bias
Circuitry Equivalent Noise Model
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VDD
DUT
Iout
Use superposition to find
contribution of each noise
source to output noise current
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Vn1
LPF
Vg
Rf
Vn2
In1
In,ch
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Cf
LPF C
Rs
Inr
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System achieves total
output noise current on the
order of 100 pA/√Hz
ADIML
Choose Cs to attenuate all noise
sources appropriately
Assuming large Cs, in1, vn1, inr
are made negligible
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Amplifier with low vn2 was
chosen
JFETs have naturally low in,ch
RIT
Analog Circuitry – LNA Noise
Contribution
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ADIML
Noise Analysis of LNA dictates
that an amp with a low input
voltage noise is chosen
Total noise contribution found to
be 25 pV/√Hz with AD797 amp
RIT
EMI/RFI Enclosure
ADIML
RIT
EMI/RFI Enclosure
ADIML
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Digital Hardware
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Xilinx Coolrunner II CPLD
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Chose Peripherals with Serial Interface
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ADIML
No internal oscillators
Flexible I/O (Voltage levels, current drive, 33 I/O pins)
Low Cost (< $3)
Familiarity with design environment
Kept CPLD resource usage low (risk of running out of logic)
Allowed communication protocols to be implemented in
software
AD5754BREZ DAC
Maxim MAX1248 ADC
On-Semi AMIS 39101 Relay Drivers
Used a CPLD register for power control lines
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CPLD Design
ADIML
RIT
Control Software
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Developed using LabVIEW
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Initial effort at learning the language difficult
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Developed highly modular code
Large hierarchy of Virtual Instruments makes high-level
modifications easy
Implements peripheral-specific protocols in LabVIEW code
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ADIML
Reaping the benefits now (easy maintenance)
Should make adding additional functionality easier than modifying CPLD
hardware or microcontroller firmware
Each register, whether located in the CPLD or a peripheral has a
VI which makes setting parameters easy (top level module
performs no protocol or bit setting operations)
Easy interface with Dynamic Signal Analyzer and 6501 USB
DAQ
RIT
Hardware/Software Testing
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Initial testing performed without any hardware
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Oscilloscope to verify software
Simulations to verify CPLD design
Once PCB arrived and was assembled hardware testing
began
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Experienced typical hiccups
Verified functionality of CPLD communication and control of
power bits
Only design error was an incorrect pinout of JTAG header
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ADIML
Fixed using Xilinx flying leads connector
RIT
Schedule
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PCB build was delayed several weeks due to several issues:
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Soldering was extra work due to lack of solder mask and high
component density
Circuit bugs due to schematic entry error (ExpressPCB has no
simulator)
Circuit bugs due to design errors
PCB reworks
Full functional/specification testing delayed due to circuit
board bugs
Mechanical design delayed due to extracurricular
circumstances
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ADIML
On track to be finished very soon
RIT
Budget
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EMI Enclosure Materials
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NI6501A USB DAQ: $100
Electrical Components: $340
PC Board: $60, +$100 for final version
Batteries and Charging Solution: $70
Total: $855
Not accounted for:
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ADIML
Metal: $150
RF Glass and Gasket: $30
JB Weld: $5
NI LabView License
Xilinx CPLD Programming Cable: $295
Probe Card: $500 ~ $1000, depending on application
RIT
Current Status
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Mechanical design fits on probe station and meets all
specifications
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Scheduled for completion
Still finding bugs in the circuit
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ADIML
Pin-compatible, rail-to-rail amps are available
If that allows the circuit to work, the final PCB can be ordered
Simulations indicate that this was the problem
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Digital Hardware / Software
Status
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CPLD modifications for new relay drivers complete
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Control Software needs updating for new relay drivers
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Was pending completion of PCB v2 layout
Need to perform hardware validation of DAC control
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ADIML
Including Simulations
DAC has never been soldered to board
Oscilloscope measurements at the right CPLD pins looked
correct
RIT
References
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ADIML
[1] Johns, David A. and Ken Martin. Analog Integrated Circuit
Design. John Wiley and Sons. 1997.
[2] Stanford Research Systems. Model SR570 – Low Noise Current
Preamplifer. SRS, Inc. 1997.
[3] Kwok K. Hung, et. Al. A Physics Based MOSFET Noise Model
for Circuit Simulators. IEEE Trans. On Electron Devices. Vol. 37.
May 1990.
RIT
Acknowledgements
ADIML
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Dr. Robert J. Bowman, Faculty Advisor and Principal Investigator
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Professor George Slack, Faculty Mentor and Guide
RIT