Sigma Delta A/D converters

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Transcript Sigma Delta A/D converters

Sigma Delta A/D Converter
e[n]
x(t)
Bandlimited to fo
Sampler
fs
x[n]
Modulator
fs
y[n]
Decimation
Filter
2 fo
16 bits
Digital
Analog
 fs
Over Sampling Ratio = 
2f
2fo is Nyquist frequency o




Transfer function for an Lth order modulator given by
L

1


Y ( z )  X ( z )  1  z  E ( z )


Modulator Characteristics
Y ( z)
• Highpass character for noise transfer function:
E ( z)
• In-band noise power is given by
 
 2 f o 


no  erms 
 2 L  1  f s 
L
•
•
•
•
L  0.5
no falls by 3(2L+1) for doubling of Over Sampling Ratio
L+0.5 bits of resolution for doubling of Over Sampling Ratio
no essentially is uncorrelated for L  2
Dithering is used to decorrelate quantization noise
Implementation
• Select Over Sampling Ratio and L such that quantization
noise is not the limiting factor
• Switched capacitor circuits
– easy to build in a digital CMOS process
– gains and time constants decided by capacitor ratios and clock frequency
• Fully differential circuits achieve better power supply
rejection and common mode noise rejection
• Analog characteristics are very sensitive to layout
– layouts are made symmetrical to overcome variations in process
Influence of Circuit Parameters
• Infinite DC gain for the integrators is unrealistic
– Finite DC gain (“integrator leakage”) causes DC offset and increased
baseband noise
– Always build the best possible op-amp for the first integrator
• Non-linearity in the feedback D/A converter
– Harmonic distortion in the output signal
– Possible modulation of the reference voltage (bad!!)
– A simple 2 level D/A (two switches and a reference voltage) is used
• Circuit noise is usually the performance limiting factor
– kT/C noise in the capacitors
– kTR noise in the resistors and switches
– Thermal and 1/f noise in the MOSFETS
Example Implementation
Decimation
• Sample rate conversion from a high rate to Nyquist rate
• Performed using cascaded digital FIR filters
• One class of filters used are called CICs (cascaded
integrator comb filters) with the transfer function
H ( z) 
 1 

1 
1 z 
K
1 1 z

2 
N  1  z 1
N
N



K
1  z 
N K
• Bit-width of the stage is given by K log 2 N   b ;‘b’ is the
output of the modulator
• Decimation in stages to ease hardware implementation
• Typically, K  L  1
Sigma Delta D/A Converters
• Modulator loop is digital
• Theory and math applicable exactly: quantization error is
replaced by truncation error
• Interpolation filter instead of sampler to raise sample rate
• Analog part: A 1 bit D/A followed by one or more filters
– Harder to build than A/D counterparts (!!) (analog part has no feedback
loop to take advantage of)
– Switched capacitor D/As, Current steering D/As are popular
– Switched capacitor filters followed by a continuous time smoothing filter
– Tapped delay line FIR filters are also used (tends to be larger in area)
General Circuit Considerations
• Keep analog and digital circuitry on separate power
supplies and spaced as far as possible
• Use the biggest capacitors possible (area and loading on
amplifiers are issues)
• Use the smallest switches possible (lower noise, lower
parasitic capacitive coupling)
• Low thermal and 1/f noise in op-amps
• Keep signal level as large as possible in the signal path
• Keep the reference voltage clean (easier said than done!!)