Transcript Slides - Agenda Catania

LHCf Collaboration Meeting - Catania
Optimization of PACE3
parameters
Sergio Ricciarini & Andrea Viciani
on behalf of LHCf Si tracker group
INFN Florence
Catania – 3 July 2009
Ricciarini & Viciani
Summary
 Description of PACE3 operation.
 Optimization of PACE3 parameters to increase dynamic range.
 Analysis of PACE3 output data to understand features.
Catania – 3 July 2009
Ricciarini & Viciani
Description of PACE3 operation
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PACE chip
 Two indipendent ASIC’s.
 Delta contains the frontend preamplifiers,
shapers and calibration circuitry.
 PACE AM contains the analog memory
(switched capacitor array), multiplexer 32:1
and readout amplifiers.
Developed for preshower of CMS (ECAL)
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Technology 0.25mm CMOS.
BGA package 15x15 mm2.
Consumption < 600 W.
Operates at the LHC bunch crossing.
frequency (40MHz).
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32 channels.
192x32 analog pipeline.
Multiplexed differential analog readout.
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~ 32 ns peaking time.
3 subsequent samples (25 ns apart from each
other) stored per LV1 trigger.
LV1 latency 3.2µs programmable.
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High dynamic range (~400 MIP) .
Two gain settings.
– High gain (0-50 MIP).
– Low gain (0-400 MIP).
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Programmable internal DACs for
biases/currents
Programmability through I2C.
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PACE3 interface timing diagram
 After 20 clock cycles from LV1, the chip
sends analog data out.
 DataValid rises and the 8-bit of the column
address (ColAddr) are streamed out (at 40
MHz), then the 32 analog channels are
streamed out (at 20 MHz).
 This cycle is repeated for the selected 3
subsequent columns of analog memory
cells.
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Time
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Analog Channel
Analog parameters (current and voltage) are controlled by DAC registers
programmable through I2C commands.
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Example: VShifter analog parameter
• Scan of 12 PACE chips (32 channels each), with calibration pulse for one channel.
• Red: all PACE chips with standard parameter value.
• Green: parameter value changed for each PACE chip.
pedestal
noise
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Example: VOutBuf
pedestal
noise
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Optimization of PACE3 parameters
to increase dynamic range
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Pedestals: preliminary study by R. Giordano (Catania Degree student)
Blu: standard parameter values
Red: preliminary parameter values derived from study over a subset of PACE chips
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• The preliminary parameter values are not good for all
chips: some chips are too near saturation (very low noise).
Noise with standard parameters
Noise with preliminary parameters
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Pedestals: final study by A. Viciani
Green: preliminary parameter values
Blue: final parameter values. The dynamic range is reduced but...
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... but now the noise values are good (~ 3 counts)
for all chips (no saturation).
well known power-up problem,
which usually disappears
when temperature increases
these other features have
been investigated as
explained in what
follows
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Further analysis of PACE3 calibration
data to understand noise features
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Noise: run 512, SPS beam test 2007
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FIRST FEATURE
Single internal channel
with high noise
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Layer 4Y: pedestal and noise for the 3 read-out columns
(3 samplings, inside PACE chip, separated by 25 ns)
Actually
optic-fibre
transmitters
read-out
boards
operate at
Hint thatthe
that
the amount
of noise ononthis
anomalous
channel
10
MHz (4on· 25
ns cycling
andcycles
with fixed
run)
depends
number
of 25time)
ns clock
after (run
LV1 by
trigger
phase relation with respect
to the 25 ns LV1 trigger pulse
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Layer 4Y: noise of the 3 read-out columns, for 4 runs taken
with the 4 possible phase relations between the 25 ns LV1
trigger pulse and the 100 ns optic-fibre transmitter clock
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Noise: run 512, SPS beam test 2007
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SECOND FEATURE
for several sensors the external
channels are more noisy
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By investigating pedestals of these noisy external channels we found
that the feature is actually a pedestal shift for half events.
Also this feature is probably noise induced by FE operation (all
ADC’s work at 20 MHz, 50 ns cycle) and enhanced for border
strips which are not completely shielded by adjacent strips.
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Conclusions
 PACE3 parameters have been optimized to increase dynamic range.
 PACE3 output data have been studied to understand features.
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