Transcript timepix-tot
Vertex detection for the Future 16/12/2009 Martin van Beuzekom 1 Outline Current vertex detectors Requirements for future vertex detectors Sensor technologies Basics of pixel readout circuits A brief look at ATLAS and LHCb pixel chips Some technological developments Summary 16/12/2009 Martin van Beuzekom 2 Current vertex detectors ATLAS ALICE LHCb • 80 M hybrid pixels • 6 M silicon strips, • planar n-in-n silicon • binary readout • 100 kHz trigger freq. • 50 mm from beam • 9.8 M hybrid pixels • 2.7 M silicon strips • planar p-in-n silicon • binary/digitized readout • kHz trigger freq. • 39 mm from beam • 1.1 % X0 / pixel layer! -----• 180 k silicon strips • planar n-in-n silicon • analog readout • 1.1 MHz trigger freq. • 8 mm from beam 16/12/2009 Martin van Beuzekom 3 Requirements for LHC detector upgrades 10x higher luminosity ◦ ◦ ◦ ◦ Finer granularity to keep occupancies low Radiation hardness up to 1016 neq/cm2 for sensors and 500 MRad TID for electronics Higher readout bandwidth LHCb: no more hardware trigger ◦ Readout at 40 MHz: “All data to farm” Reduce inefficiencies ◦ Mainly due to readout chips Less material + least power ◦ Thinning of sensors and readout chips ◦ Use of CO2 cooling ◦ Power cabling bottleneck, on chip converters or serial powering 16/12/2009 Martin van Beuzekom 4 Future vertex detectors: ILC/CLIC Low duty cycle beams ~ 1 ms 200 ms ◦ ILC peak luminosity similar to LHC ◦ Acquire hits during beam pulse, readout later ◦ Much less radiation damage Single point resolution < 3 um ◦ Low material budget; X0 < 0.2% per layer ◦ Cooling by gas flow -> low power electronics Great opportunity for monolithic pixel detectors ◦ MAPS, DEPFET, ISIS, CCD -> Jan Timmerman’s talk 16/12/2009 Martin van Beuzekom 5 Hybrid pixel detector + + + + - sensor 100 – 300 um 750 um Readout chip . Sensor material depends on application Hybrid Pixel ◦ Silicon, gas or diamond for High Energy Physics ◦ Silicon, GaAs, CdTe, etc. for imaging 16/12/2009 Martin van Beuzekom 6 Monolithic Active Pixel Sensors p+ substrate + p-epi + + - Deep n-well technology - Basic Monolithic Active Pixel - Only ~ 1000e- signal from epi layer But also very low noise No drift field -> slow charge collection Very low mass 10-15 mm Limited radiation hardness Low speed Low price p-well n-well ◦ Better charge collection ◦ More electronics on chip (intelligence) 16/12/2009 Martin van Beuzekom 7 Sensor technologies for LHC upgrades Key requirements: Rad. hardness, resolution, small dead area planar Planar silicon ◦ Operation at very high voltage after irradiation ◦ High leakage current -> low temp. operation ◦ Cheap -> replace inner layers at regular intervals Planar diamond E 3D ◦ No leakage current -> room temperature operation ◦ Expensive, so far only cm2 size single crystals ◦ Excellent thermal conductivity 3D silicon E ◦ Short charge collection distance -> low bias voltage ◦ Active sensor up to edge. Complex (expensive) processing Gaseous detectors (Martin Fransen’s talk) 16/12/2009 Martin van Beuzekom 8 Radiation hardness of semiconductor sensors Silicon: Signal loss due to charge trapping Increased leakage current Higher full depletion voltage ◦ Partial depletion at end of life Diamond: Charge collection distance reduces with fluence Same for polycrystaline and single crystal diamond S/N is figure of merit sLHC 16/12/2009 ◦ Diamond has lower noise Martin van Beuzekom 9 Generic pixel chip architecture Typical pixel sizes for HEP ◦ 50x400 mm2 (current ATLAS) ◦ 150x150 mm2 (current CMS) ◦ 50x250 mm2 (ATLAS IBL upgrade) Pixel array “standard” pixel size for imaging ◦ 55x55 mm2 (Medipix / Timepix) End of column logic DACs serializer Dead area 5 .. 15 % 3 sides buttable I/O 16/12/2009 Martin van Beuzekom 10 Column readout pixel pixel Token passing scheme: • To initiate readout • Bus arbitration 256 .. 336 pixels pixel pixel pixel pixel token Column interface Buffer Row interface Row interface 16/12/2009 Row interface Martin van Beuzekom 11 Pixel functionality Preamp + discriminator Time Over Threshold (TOT) measurement (ADC) Time Of Arrival (TOA) measurement Buffer equalizes peak rates ◦ Number of hits fluctuates in time ◦ Limited depth -> inefficiencies optional TOT TOA Vth preamp column interface discr. buffer A single hit generates ~25 bits of data 16/12/2009 Martin van Beuzekom 12 Time Over Threshold / Time Of Arrival Q(t) thr time Discriminator out Shutter /trigger clock TOT TOA Fine time Time over Threshold gives a measure of deposited energy Time of arrival: common stop TDC (attach Bunch crossing ID label) ◦ Fine time for applications with drift gas like TPC 16/12/2009 Martin van Beuzekom 13 Atlas pixel chip developments for IBL sLHC FE-I4 is successor of FE-I3, 50x250 mm pixels, 130 nm Radiation level 200 MRad TID ~200 Mhits /cm2 /s FE-I3 > 99 % of data is not read out Main limitation of FE-I3 is data traffic in column IBL Collaboration between LBNL, Bonn, Genova, Marseille, Nikhef Inefficiency Additional benefit: lower power LHC ◦ solution: use pixel level buffers Hit prob. / DC The “inefficiency wall” 16/12/2009 Martin van Beuzekom 14 FE-I4 Shared Digital Part 19 mm 80 cols X 336 Rows Trigger Logic DATA Local Buffer Control Clustering Logic • 5 buffers per 4 pixels • 0.05% inefficiency from buffer overflow • 0.5% inefficiency from double hit • Only read data after trigger sLHC : > 1 GHz/cm2 pixel hits 16/12/2009 V. Gromov, R. Kluit, J.D. Schipper, V. Zivkovic 20 mm • Largest chip in HEP: 19 x 20 mm • 90 % active area • Chip submission expected Jan 2010 • Testing such large chips is not trivial Martin van Beuzekom 15 LHCb vertex detector upgrade Pixels instead of strips! Pixel readout chip based on Timepix/Medipix Completely different digital readout needed 256 x 256 pixels 55 mm square. Small pixel cell means that single sided modules can be built By using TSV (through silicon vias) dead side can be reduced to 0.8 mm in Medipix3 Radiation hardness of Medipix3 is 500 MRad 4 bit equivalent ADC resolution provided via TOT Upgrade being considered to 90 nm technology (more functionality, power consumption and radiation hardness benefits) 16/12/2009 Martin van Beuzekom 14100 14100 800 Medipix3 Chip dimensions 16 Timepix testbeam results Telescope planes at 9 degrees Excellent position resolution due to centroiding Unbiassed residual [um] Timepix: 55 mm pitch PRELIMINARY Estimated track contribution to residual 2.5 mm Track angle (degrees) 16/12/2009 Martin van Beuzekom 17 VELO pixel readout challenge Pixels only ~ 7 mm from beam ~ 200 Mhits/cm2/sec and no trigger! average particle rate per bx and average data rates (Gbit/s) ◦ 2 to 3 pixel hits per particle-hit 1.3 0.9 -> 10 .. 15 Gbit/s for chip closest to the beam 4.5 3.4 Readout architecture studied in ‘Kenniswerkers Nikhef + Bruco B.V Borne’ 4.6 1.7 13.2 5.5 Particle Hits / Event / cm2 ◦ Assuming 22 bits per hit LHC beam 5.8 1.4 16.4 4.7 JC Wang 7 mm L=2E33 L=2E32 radius (cm) 4.6 1.7 13.2 5.5 1.4 0.9 4.5 3.4 -> Tom Sluijk’s talk on high speed readout 16/12/2009 Martin van Beuzekom 18 Through Silicon Vias (TSV) sensor TSV Connection from front to back of chip Front of chip for sensor connection Back of chip hosts all interfaces TSV process ◦ Etch hole (Deep Reactive Ion Etching) ◦ Passivate and plate with copper Readout chip . Typical hole diameter 20 - 50 um Aspect ratios ~10:1 Becoming industry standard process! Printed circuit board 16/12/2009 Martin van Beuzekom 19 Future: Vertical (3D) integration Why limit yourself to 2 layers? 3D technology driven by industry ◦ Lower L, R, C and hence higher speed / lower power ◦ ‘electronic cube’ Thinning down chips to 7 – 20 micron Different technology for analog and digital layer Under investigation for ILC pixel detector 3-D Pixel Sensor pixel Analog Digital 16/12/2009 Martin van Beuzekom 20 Summary Requirements for future vertex detectors are demanding Extreme radiation levels for sLHC will reduce semiconductor detector signals ◦ No clear sensor candidate: planar Si, 3D-Si, Diamond or gas… FE-I4 chip for ATLAS exists ◦ Can handle 200 Mhits/cm2 /s with only 0.6% inefficiency LHCb vertex detector group investigates pixels ◦ Timepix chip as starting point ◦ Readout of 15 Gbit/s per chip is a challenge Longer future: vertical (3D) integration gives many new possibilities Yearly conference dedicated to vertex detectors: next one is Vertex2010 in Scotland 16/12/2009 Martin van Beuzekom 21 16/12/2009 Martin van Beuzekom 22 Intermezzo: Vertex + Timepix TIMEPIX-TOT in H6 PION BEAM BRAGG PEAK at END of TRAILS FULL FRAME 256x256 PIXELS INTERACTION with ENERGY DEPOSIT MEASUREMENT LARGE ENERGY DEPOSIT at VERTEX DELTA RAYS EMITTED SEPARATELY VISIBLE IF > 30keV PION BEAM DELTA RAYS may SHIFT DATA POINTS M.I.P. TYPICALLY DEPOSITS 200 - 300 eV per um 11- 16.5 keV in PIXEL TIMEPIX TOT RANGE 70-95 (1keV~6) Erik HEIJNE CERN PH Dept 16/12/2009 Martin van Beuzekom 23 Chip technology 130 nm or 90 nm ◦ Shown to be radiation hard up to 500 Mrad Even for standard digital library cells Smaller technologies might be not as radiation hard, high-k dielectric 16/12/2009 Martin van Beuzekom 24 ISIS2 Cross Section 16/12/2009 Martin van Beuzekom 25 16/12/2009 Martin van Beuzekom 26