Transcript Introduction

Status of the CARIOCA project
Walter Bonivento
CERN / INFN Cagliari
for the LHCb collaboration
and the CERN MIC group
LEB Conference, Stockholm 2001
The LHCb muon
detector
LHCb muon detector: main task
provide L0 trigger for b   X
Five stations, M1 to M5; four radial regions, R1 to R4
R3-R4 of M4-M5 RPC 48% area
rate cap. 1kHz/cm2
R1-R2 of M1
the rest
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t.b.d. 1% area
rate cap. 1MHz/cm2
MWPC 52% area
rate cap. 100kHz/cm2
Readout electronics
for MWPC:
a) detector architecture
Main performance requirement:
efficiency in 20ns >99%
2 bi-gap logically OR-ed
(DIALOG chip)
2mm gap, 1.5mm wire spacing
wire, cathode and combined
readout
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Readout electronics
for MWPC:
b) requirements
Detector signal: current with fast (ns) rise,
1
fall
t (ns )  1.5
Detector capacitance from 20pF to 200pF
One threshold for time stamping: time resolution from slewing effect
Optimum amplifier peaking time
compromise between
noise and slewing
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Readout electronics
for MWPC:
b) requirements
Measurements on a
prototype chamber
performed with a
hybrid from PNPI and
a modified version of
ASDQ chip
(M.Newcomer-Penn)
Optimum amplifier
peaking time: about 10ns
At large Cdet weak
dependence of time
resolution on peaking time
To be able to set the
threshold at about 6 p.e.
noise <2fC for Cdet 40-250pF
At gas gain of 105
average 40fC for wires and 20fC for cathode
range 150fC for 95% of the signals
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Readout electronics
for MWPC:
b) requirements
High rate: dead time
pulse width <50ns
unipolar and
tail cancellation
wire signals AC coupled with RLCdec= 100s
baseline shifts
Low cross-talk :
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baseline restoration
Zin< 50 
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CARIOCA
Project overview
80k FE channels at 1Mrad dose in 10 years
custom chip in radiation tolerant technology 0.25 m CMOS
Final goal: differential structure
Cancels
1/t
tail
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Cancels
preamp
tail
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CARIOCA
Project overview
PROTOTYPE CHIPS: step by step approach
•2000: positive preamp+current discriminator
+LVDS 4ch (1 analog ch.)
•2001: positive preamp+current discriminator
+LVDS 14ch
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CARIOCA
Project overview
•2001: negative preamp 8ch analog
•2001: positive preamp+shaper 4ch analog (diff. out.)
•2001: positive preamp+shaper+voltage discriminator+LVDS 4ch (diff. out.)
•2002: positive and negative full chain with baseline restorer (diff.out.)
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The positive
preamplifier:
a) design
Current amplifier NMOS with current mode feedback; unipolar
Large input transistor
W/L=1600m/0.7m
Id=2mA
Dominant pole
p1 
I OUT gmN 4

6
I IN
gmN 3
gmN 2 gmN 3 R2
C feed
at about 20MHz, the other two at
150MHz and 300MHz
Followed by current discriminator (presented at LEB2000 by D.Moraes
and replaced by a voltage discriminator in next version) +LVDS driver
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The positive
preamplifier:
b) measurements
Digital (S-curve)...
...and analog measurements
Linearity
Response to a delta
Sensitivity: 8mV/fC (measurement)
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Response to a delta
The positive
preamplifier:
b) measurements
Threshold
vs.Cd
Noise vs. Cd
Channel uniformity of noise and
threshold: 7% r.m.s.
Cross talk around 1%
ENC
= 867e- + 36e-/pF
Power consumption of about 18mW per
channel dominated by
LVDS driver
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Analog measurement
Digital measurement
Simulation (CADENCE)
calculation from noise
theory
The positive
preamplifier:
b) measurements
Problems of the discriminator:
1) it does not work below 10fC (need 5fC).
It was tested on a chamber prototype
efficiency plateau shifted by 100V w.r.t. to
our best measurement (with ASDQ chip).
2) it slows down the signal rise-time significantly (input C of discr.)
Peaking time
vs.Cd
7ns are
expected
from p.a.
alone
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Discriminator changed
in next versions of the chip
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The negative
preamplifier:
a) design
N2,N3,N4 replaced by PMOS
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The negative and
positive preamp:
frequency response
negative
positive
CADENCE simulation
Closed loop gain
3dB level is at:
• 16 MHz for negative
• 23 MHz for positive
Cdet=60pF
Input impedance: below 50
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The negative
preamplifier:
b) measurements
Response to a delta
Cd=15pF
Cd=100pF
Linearity
Measurements
Simulation
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The negative
preamplifier:
b) measurements
Response to a
delta
Peaking time vs. Cd
improved w.r.t first
prototype
Sensitivity
vs. Cd
Noise vs. Cd
Channel uniformity of noise
and threshold: 7% r.m.s.
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ENC= 951e- + 31e-/pF
Measurements
Simulation
The negative
preamplifier:
b) measurements
Response to a
quasi 1/t pulse
Cd=15pF
quasi 1/t injector
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Cd=100pF
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The shaper:
a) design
Folded cascode fully differential balanced (CMF)
Designed for 1ns peaking time
(not to add to the preamp)
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Dominant pole (neglecting p.z. comp)
at 160MHz
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The shaper:
a) design
• 2-pole/zero network to compensate for the 1/t tail
• basic idea from R.A.Boie et al.,NIM 192(1982)365
• adapted to a differential amplifier design (M.Newcomer, Penn)
 s  1 /  1  s  1 /  3 



s

1
/

2
s

1
/

4



 1  9ns  3  80ns
 2  3.5ns  4 40 ns
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Cdet=60pF
The shaper:
b) measurements
This prototype chip with the positive preamplifier
Response to a delta: single ended ouptut (true output will be
differential)
Cd=15pF
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Cd=100pF
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The shaper:
b) measurements
Response to a delta: single ended output (true output will be
differential). Saturation current on ( ) and off ( )
Measurements
Simulation
Linearity: improved with saturation current ON
(changes the DC level at the drain of N0)
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The shaper:
b) measurements
Response to a delta: single ended output (true output will be
differential). Saturation current on.
Cd=100pF
Cd=15pF
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The shaper:
b) measurements
Response to a delta:
single ended output
Peaking time vs. Cd.
Faster than negative
consistent with different
bandwidth
Noise vs. Cd
Measurements
Simulation
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Sensitivity
vs. Cd
ENC= 1290e- + 40e-/pF
with saturation current ON
Parallel noise term higher than
preamp alone due to two
preamplifiers at shaper input
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The shaper:
b) measurements
Response to a
quasi 1/t pulse
Cd=100pF
Cd=15pF
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The shaper:
b) measurements
Response to a
quasi 1/t pulse
Peaking time vs. Cd
Measurements
Simulation
Pulse width vs. Cd
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Sensitivity
vs. Cd
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Conclusions and
perspectives
Negative preamplifier and positive preamplifier with shaper
chips tested and satisfying the requirements for LHCb operation
• Amplifier+shaper+Voltage discriminator chip (following
ATLAS MDT chip design) under test
• +Baseline restoration chip under design
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THE END
LEB Conference, Stockholm 2001