Transcript Slides

Activities of the SOI R&D collaboration
April. 24, 2010 @VIPS2010
Yasuo Arai, KEK
[email protected]
http://rd.kek.jp/project/soi/
We miss Arai-san in the WS.
He could not come due to the
flight cancellation.
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OUTLINE
1. Introduction
2. Activities
MPW run
Pixel Detectors
Buried p-Well
Vertical Integration
Wafer Thinning
3. Summary
Technical details will also be shown by T. Miyoshi.
KEK-OKI SOI Brief History
'05. 7: Start Collaboration with OKI Semiconductor.
KEK
is supporting this R&D as the
st
'06.12: 1 (and last) 0.15 um KEK MPW run.
mostFNAL,
important
target of the KEK
(LBNL,
U of Hawaii joined)
Detector
Project
'07.3: 0.15 umTechnology
lab. process line was
closed. (KEKDTP)
--> regards
move to 0.2 also
um mass
line. activity
and
asproduction
the VIPS
st 0.2 um KEK MPW run.
'08.1:
1
agreed (@TIPP09) to be supported by
'09.2: 2nd 0.2 um KEK MPW run.
the directors of the 3 labs.
rd
'05.10: First Submission in VDEC 0.15 um MPW.
'09.8: 3 0.2 um KEK MPW run.
'10. 1: 4th 0.2 um KEK MPW run.
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SOIPIX Collaboration
• A sort of Consortium for developing radiation sensor by
using the SOI and 3D technology.
• Use common processes and share developing cost.
• Exchange information of which is common interests.
• Share common works such as evaluation of the process,
transistor characteristics, radiation hardness, library etc.
Each group has their own
target applications.
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Target Applications
• High Energy Physics
Vertex detector @ KEK, FNAL, MPI, U. Hawaii.
Belle II, ILC, sLHC, ...
• Material Science
X-ray Free Electron Laser (XFEL) @ Riken
SR application @ KEK, LBNL
....
• Astrophysics, Space applications
X-ray Imaging detector @Kyoto Univ.
SEU immune electronics @JAXA, SLAC
• Medical
Mammography, PET, Hadron Therapy, ...
• Electron Microscopy
• ...
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SOIPIX Collaboration Members
KEK : Y. Unno, S. Terada, Y. Ikegami, T. Tsuboyama, T. Kohriki, Y. Ikemoto,
T. Miyoshi, K. Tauchi, R. Ichimiya, Y. Fujita, Y. Ikemoto, D. Nio, Y. Arai
Tsukuba Univ. : K. Hara, H. Miyake, T. Sega, M. Kochiyama
Osaka Univ.: K. Hanagaki, J. Uchida, T. Idehara
Tohoku Univ. : Y. Onuki, Y. Horii, H. Yamamoto, Y. Takubo, T. Nagamine, Y. Sato
Kyoto Univ. : T. Tsuru, H. Matsumoto, S. G. Ryu
Kyoto U. of Education : R. Takashima, A. Takeda
JAXA/ISAS : H. Ikeda, D. Kobayashi, T. Wada, H. Nagata, T. Kishishita
RIKEN : T. Hatsui, T. Kudo, T. Hirono, M. Yabashi, Y. Furukawa, A. Taketani.
T. Kameshima
LBNL : M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato, L. Glesener
FNAL : G. Deptuch, R. Yarema, M. Trimpl, R. Lipton, F. Khalid
Univ. of Hawaii : G. Varner, M. Cooney, H. Sahoo, J. Kennedy
INP, Krakow : P. Kapusta, H. Palka, Imran Ahmed
INFN Padova : D. Bisello, S. Mattiazzo, D. Pantano
Louvain-la-Neuve Univ. : E. Cortina, L. Soungyee
OKI Semiconductor Co. Ltd. : I. Kurachi, K. Fukuda, ....
OKI Semiconductor Miyagi Co. Ltd. : M.Okihara, N. Kuriyama, T. Tatsumi, ....
ZyCube/T-Micro : M. Motoyoshi
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SOI Pixel Detector
Monolithic detector using
Bonded wafer (SOI :
Silicon-on-Insulator) of
Hi-R and Low-R Si layers.

No mechanical bump bondings
-> High Density, Low material budget
-> Low parasitic Capacitance, High Sensitivity

SOI pixel sensor is
Standard CMOS
circuits
can be built
two
layer
Thin active Si layer (~40 nm)
monolithic
3D
electronics
-> No Latch Up, Small SEE Cross section.
inIndustrial
its original
Based on
standardform.
technology

Seamless connection to Vertical Integration


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SOI Pixel Process Flow
SOI (40 nm)
Box (Buried
Oxide)
(200 nm)
To be covered by
Kurachi
650um
Handle Wafer
p+
n+
Handle Wafer
n+
Handle Wafer
p+
50~650um
Al
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Activities
9
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First International MPW
• Advanced semiconductor R&D is very
expensive!
ulti roject afer runs since 2006
organized by KEK.
2007
2008
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SOI MPW run web page
http://rd.kek.jp/project/soi/
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Integration Type Pixel (INTPIX4)
Largest Chip so far.
15 mm
10 mm
17x17 mm, 512x832 (~430k）pixels、13 Analog Out、CDS
circuit in each pixel.
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Counting Type Pixel (CNTPIX5)
9bit x 8
Various sensor design and
evaluations to be reported by
the following speakers. Time
Resolved
Imaging
Energy selection and
Counting in each pixel
5 x15.4 mm2
72 x 272 pixels
64um x 64 um pixel
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Back Gate Problem
Front Gate and Back
Gate areFatal
coupled.concern
(Back Gate Effect)
with SOI
technology having extremely
thin interconnection layer
between sensor and
electronics.
VTH _ front 

Cgate _ oxide
CBOX
VG _ back
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Buried p-Well (BPW) Process
BPW Implantation
Substrate Implantation
Buried
Oxide
(BOX)
SOI Si
Pixel
P+
Peripheral
BPW
• Cut Top Si and BOX
• High Dose
• Keep Top Si not affected
• Low Dose
• Suppress the back gate effect.
• Shrink pixel size without loosing sensitive area.
• Increase break down voltage with low dose region.
• Less electric field in the BOX which may improve radiation
hardness.
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Id-Vg and BPW
w/o BPW
with BPW=0V
NMOS
back channel open
shift
Back gate effect is suppressed by the BPW.
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Vertical (3D) Integration
Already reported by
Further Integration by using m-bump bonding (~5 um pitch)
Motoyoshi
technology of ZyCube Co. Ltd.
 See Motoyoshi san's Talk on the first day.
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(T-micro)
m-bumps fabrication
Copyright 2009 OKI semiconductor Co. Ltd.
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Wafer Thinning (TAIKO process)
Back side process
still can be done
after thinning.
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Thinning to 110 um
and dicing
Sensor Still Works.
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I-V Characteristic Before & After Thinning
薄化前後IV比較@INTPIX2(補正後)
i : before
s : after
1.00E-03
No difference seen
after thinning
1.00E-04
Current[A]
1.00E-05
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E-10
0
20
40
60
80
100
Voltage[V]
120
140
160
180
200
<A_a>_i
<B_a>_i
<C_a>_i
<D_a>_i
<E_a>_i
<A_a>_s
<B_a>_s
<C_a>_s
<D_a>_s
<E_a>_s
<A_b>_i
<B_b>_i
<C_b>_i
<D_b>_i
<E_b>_i
<A_b>_s
<B_b>_s
<C_b>_s
<D_b>_s
<E_b>_s
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Process Improvements (from next run)
• Increase No. of Metal Layer : 4 -> 5 layers
--> Better Power Network for Large Chip
• Increase MIM Capacitance : 1 -> 1.5 fF/um2
--> Shrink Pixel size
• Relax drawing rule : 30o, 45o -> Circle
--> Higher Break Down Voltage
• Buried N-Well Test
• Introduction of source‐inserted body
contacts
--> Better body contacts
Next MPW run is scheduled at
the end of July.
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Summary
• SOI project has passed 5 years after start, and many
users are participating the MPW run now.
• Buried p-Well technology is very successful to suppress
the Back Gate problem.
• Vertical (3D) integration is one of the key technology
for future pixel detector.
• Thinning by TAICO process is very promising.
• We are operating SOI MPW run twice per year.
• We need more and more participants to make the
technology further established.
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You are welcome to
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