Transcript ppt - Belle II

Status of SOI Pixel Development
July 8, 2009
@Belle II, PXD Mtg.
Yasuo Arai (KEK)
[email protected]
http://rd.kek.jp/project/soi/
•Multi Project Wafer run schedule
•SBPIX1 Test
•Buried p-Well Test
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Call for SOI Multi Project Wafer (MPW) run
through Facilitation Group
Dear colleagues,
You may know that a facilitation group for monolithic and vertically
integrated pixel sensors’ has been established by the three Regional
Directors (CERN, FNAL and KEK) ...
On behalf the ‘facilitation group for monolithic and vertically integrated
pixel sensors’ (Marcel Demarteau, Junji Haba, Hans-Günther Moser
and Valerio Re) we would like to announce an offer from KEK to
participate in a MPW run with OKI. ....
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FY2009 MPW Schedule
*1st MPW: submission on 7th Aug. 2009
*2nd MPW: submission on end. Oct. 2010
*3rd MPW: submission on beg. Jan. 2010
We have received several contacts from foreign labs ;
India, UK, Spain, USA, Poland ...
Cross Section of Silicon-On-Insulator Pixel
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SBPIX1 : First Test Chip for Belle II
By Yasuyuki Horii
SBPIX1
First Test chip for Belle II
5 mm x 5 mm
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SBPIX1 Pixel
Trigger Latency
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First Image taken by Laser Light
Beam test is under
planning.
Sum for 3000 events.
Latest Chips submitted on Feb. 2009
p/n Implant and Buried P-Well (BPW)
B (~1E12 cm-2)
B or P(~5E15cm-2)
Buried
Oxide
SOI Si
PSUB
BPW
• Cut Top Si
• Keep Top Si
• High Dose
• Low Dose
Suppression of Back Gate Effect with BPW
Without BPW
With BPW
Vback Up
BPW Layer is very effective to suppress back gate effect.
Effect on Transistor Characteristic
There are very little changes in the Transistor characteristics
due to the BPW Implantation.
Summary
• We will have 3 MPW run in this fiscal year, and call for
SOI MPW run was done through the Facilitation group.
• First image was taken with SBPIX1 chip.
• Back gate effect was dramatically suppressed with BPW
layer.
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