Transcript Section 1

Abderrezak Mekkaoui
[email protected]
General Outline




Introduction
A glance at the current ITRS roadmap for analog
Some 65nm device test results
Some examples of current projects





FEI4 (ATLAS)
ATPIX65 (LBNL)
APSEL(INFN)
MAPS (LBNL)
HIPPO (LBNL)
 Vertical integration: 3D
 Conclusions
 Backup slides and extras
NOTE: throughout this presentation, HEP denotes High Energy Physics and similar fields
2
Introduction
Performance and functionality of integrated circuits continued to increase for the past few
decades. Technology scaling (down) has fueled what is known as Moore’s law (or is it vice
versa?): the number of components per chip roughly doubles every 24 months.
Transistor dimensions (width, length and gate thickness) are continuously decreased
and so are the metal pitch while the number of metal levels has been increased. Process
optimization for some niche market (like RF) has also led to multi-threshold and multisupply transistors along with high quality passives.
While scaling down is still going on, industry experts are already introducing the concept
of “more than Moore” to prevent the increase of performance of ICs from slowing down
(physical scaling down will ultimately be unpractical).
Without the advances in IC technology, some important HEP projects (at some crucial
time) would have been not feasible or would have required specialized low yield low
performance high cost processes.
The future will be no different. Complex and challenging instrumentation projects
(Upgrades, SLHS, new Detector concepts) will require the adoption of the ever more
empowering (and more complex) IC technologies. This is exemplified by recent design
activities using the 65nm CMOS node, which is the state of the art for this community. This
talk will briefly describe some of the prototyping work in 65nm CMOS (mainly).
3
Industry and HEP IC “nodes”
250nm, 70Mrad special layout
130nm, 250Mrad
65nm, >200Mrad
A. Baschirotto, University of Milano-Bicocca
“LV Analog Design in scaled CMOS technology”
(image without the HEP figures)
HEP projects, even though lagging mainstream technology, are benefitting from
Technology scaling. There should be a “topical” Moore’s law.
ICs are only one part of an instrumentation system! Is detector technology not keeping pace?
4
ITRS performance RF/Analog roadmap
Year of Production 
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
Supply voltage (V)
1.1 1.05 1.05 1.05
1
0.95 0.95 0.95 0.85 0.85 0.85 0.85 0.75
Tox (nm)
1.2
1.2
1.2
1.2 1.10 1.10 1.10 1.10 1.10 1.00 1.00 0.90 0.90
Gate Length (nm)
38
38
32
29
27
22
18
17
15
14
13
12
11
gm/gds at 5·Lmin-digital
30
30
30
30
30
30
30
30
30
30
30
30
30
1/f-noise (µV²·µm²/Hz)
100
90
80
70
70
60
50
50
40
40
40
30
30
s Vth matching (mV·µm)
5
5
5
5
5
5
5
5
5
5
5
4
4
Ids (µA/µm)
9
9
8
7
7
6
5
4
4
3
3
3
2
Peak Ft (GHz)
240 240 280 310 340 400 480 520 570 630 680 750 820
Peak Fmax (GHz)
290 290 340 380 420 510 610 670 740 820 900 990 1090
NFmin (dB)
0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2
Notice difference between Performance versus precision (next slide)
ITRS key: Yellow=solution known but not optimized. Red= solution not known.
http://www.itrs.net/
5
ITRS Precision Analog/RF roadmap
Year of Production 
Supply voltage (V)
Tox (nm)
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
2.5
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.5
1.5
1.5
5
3
3
3
3
3
3
3
3
3
2.6
2.6
2.6
Gate Length (nm)
250 180 180 180 180 180 180 180 180 180 130 130 130
gm/gds at 10·Lmin-digital
220 160 160 160 160 160 160 160 160 160
1/f Noise (µV²·µm²/Hz)
100
360 360 360 360 360 360 360 360 360 270 270 270
0
110
110
110
s Vth matching (mV·µm)
9
6
6
6
6
6
6
6
6
6
5
5
5
Peak Ft (GHz)
40
50
50
50
50
50
50
50
50
50
70
70
70
Peak Fmax (GHz)
70
90
90
90
90
90
90
90
90
90
120 120 120
Tox decreasing: better ionizing radiation resistance. Gate rupture? Other problems?
Gm/gds decreasing: Lower gain
1/f noise decreasing.
Matching improving (barely and only for analog devices)
Speed increasing
Supply voltage decreasing: reduced Dynamic range.
Other: gate leakage, off current, variability of non analog transistors …
6
The main design challenges (my experience)
Gate leakage
Big problem biasing/controlling large
number of transistors in parallel
(pixels).
Current is proportional to gate area:
can be problematic for low noise large
cap FENDs (wide input transistor)
Be Aware the problem. Can be serious.
Realistic simulations is a must. Design
Bias DACs to handle the excess current.
Use higher voltage devices, if possible
(be aware of radiation issues).
Off leakage
current
Problem for low current circuits. May
lead to higher power (increase
operating currents to dwarf leakage)
Use low leakage transistor variants
(order of magnitude lower).
Creatively live with it.
Low Supply
voltage
Reduced Dynamic range. May lead to
higher analog power. Problem for high
precision/accuracy systems
Use rail to rail circuits. LV circuits
techniques…
Highly layout
dependent
device
parameters
Makes design more complex. Requires
a high quality design kit
Read the manuals (obvious but …).
Check the effects are back annotated
for simulations.
It is only a problem of degree. Analog design has always been about designing working
circuits using imperfect devices. Good circuits were designed in NMOS only single metal
Single poly processes! Read IEEE JSSC!
7
ITRS bipolar Roadmap
Year of Production
1/f-noise (µV²·µm²/Hz)
s current matching (%·µm)
High Speed NPN (HS NPN) Common to mmWave Table
Emitter width (nm)
Peak fT (GHz)
Peak fMAX (GHz)
Maximum Available Gain
(dB) @ 60 GHz
Maximum Available Gain
(dB) @ 94 GHz
NFMIN (dB) @ 60 GHz
BVCEO (V)
JC at Peak fT (mA/µm2)
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
2
2
1.5
2
1.5
2
1.5
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
130
265
310
120
285
350
110
305
390
105
325
430
95
345
470
90
365
510
85
385
550
80
405
590
75
425
630
70
445
670
65
465
710
65
485
750
60
505
790
12.0 12.9 13.6 14.3 15.0 15.6 16.1 16.6 17.1 17.5 18.0 18.4 18.7
8.0
8.9
9.6
10.3 11.0 11.6 12.1 12.6 13.1 13.5 14.0 14.4 14.7
2.5
1.7
14
2.0
1.7
15
1.6
1.6
16
1.3
1.6
18
1.1
1.5
19
0.9
1.5
20
0.8
1.4
22
0.7
1.4
23
0.6
1.4
24
0.5
1.3
26
0.5
1.3
27
0.4
1.3
28
0.4
1.2
30
500
25
40
5.5
500
40
50
4.0
300
60
80
3.0
300
80
90
2.5
200
85
95
2.2
200
95
105
2.0
200
105
115
1.9
200
115
130
1.8
200
125
140
1.7
150
135
150
1.6
150
145
160
1.5
150
155
170
1.4
150
165
180
1.4
High Speed PNP (HS PNP)
Emitter width (nm)
Peak fT (GHz)
Peak fMAX (GHz)
BVCEO (V)
For specialized projects.
Main challenge: breakdown voltage getting lower.
8
Advanced IC processes are available thru brokers
32 nm
0.9 /1.5
7th generation IBM SOI technology improves energy savings for highperformance servers, printers, storage devices; networking, mobile, consumer,
and game applications. Trusted foundry access only.1
IBM CMOS (mosis)
45 nm
1.0 /0.9
This energy-saving SOI process is suitable for a broader range of consumer
electronics, including digital TVs and high-end mobile applications. Trusted
foundry access only.1
65 nm 1.0 /1.8, 2.5 Excellent for consumer electronics, wireless communications, and other
applications requiring high performance or system-on-a-chip. Trusted foundry
access only.1
90 nm
130
nm
1.2 /2.5
Tailored for power-sensitive applications in wireless communications and
consumer electronics. Trusted foundry access only.1
1.0 /2.5
Ideal for leading-edge microprocessors, communications, and computer data
processing applications. Trusted foundry access only.1
1.2 /2.5
40 Low-power
Use for low-cost, high performance wireless applications, as Bluetooth,
WLAN,logic
nm
cellular handsets, mobile TV, WiMax, UWB and GPS. Trusted foundry
access only.1
65 Standard
logic, RPO
Use for low-cost, high performance wireless applications as Bluetooth,
WLAN,
nm Mixed-mode/RF, RPO, MiM
cellular handsets and GPS.
90 Standard logic, RPO
Similar to 8RF-DM, but uses LM top metal.
nm Mixed-mode/RF, RPO, MiM
0.13 Standard logic, RPO
µm Mixed-mode, RPO, MiM
Low-power logic, RPO
TSMC CMOS (mosis)
Low-voltage logic, RPO
1.2 /2.5
1.2 /2.5
VDD
9
Advanced IC processes available thru brokers
IBM SiGe BiCMOS Processes
Feature CMOS
SiGe
Size Vdd [V] Ft [GHz] | BVceo(1) [V]
HP
HB
Ft/BVceo Ft/BVceo
0.13 µm 1.2, 2.5, 200 | 1.77
3.3
1.2, 2.5, 103 | 2.4
3.3
0.18 µm 1.8, 2.5, 120 | 2.0
3.3
1.8, 2.5, 60 | 3.3
3.3
0.25 µm 2.5, 3.3 47 | 3.3
2.5, 3.3
60 | 3.2
Description
IBM BiCMOS SiGe (mosis)
57 | 3.55 5th generation SiGe technology for advanced RADAR and mmWave
applications.
54 | 4.7 Reduced performance, cost effective technology for wireless applications.
20 | 4.75 4th generation SiGe technology best suited for wireless and high-speed
switches.
29 | 6.0 Reduced performance, yet most cost effective SiGe technology offered.
27 | 5.7 3rd generation SiGe technology.
29 | 6.0 A descendant of 7WL, it integrates 0.25 µm CMOS with the 7WL SiGe NPN.
28 nm CMOS28LP
CMOS 7LM
40 nm CMOS040
CMOS 7LM
65 nm CMOS065
CMOS 7LM
65 nm CMOS065-SOI SOI 6LM
St Micro CMOS (cmp)
Other less advanced and specialized processes
are available thru mosis, cmp, europractice
And others!
http://www.mosis.com
http://cmp.imag.fr/
http://www.europractice-ic.com/
10
Area reduction Highest for mostly digital systems
For analog design, most of the challenges can be addressed by proper device
selection and design. But at the expense of increased area: Reduce analog
functionality to the minimum to benefit from the ever increasing integration
density in advanced process. Analog “deficiencies” can be mitigated by special
digital techniques.
Die area reduction based on analog/digital mix (A. Baschirotto )
11
Harnessing digital processing power (a physicist perspective)


Complex pattern recognition on chip

Cluster formation, including NN-style.

Rejection of background clusters- eg. from beam halo particles

Generic user-programmable DSP
Pulse shape analysis.



Self-repairing or self-testing designs. Either 100% yield or chips that automatically
report their quality upon power-up (second probably easier)
Self calibrating, self timing-in, etc.




Digital corrections for anything and everything (eg. Time-walk).
No need to save and download threshold tunes, for example, because threshold
is automatically tuned on-chip in real time.
Automating monitoring, interlocking, etc.
Configurable geometry. Not all pixels have to be used. User selects desired density
lower density = lower power and greater bump bonding pitch
Prompt hit processing (complex and fast processing of hits from pixel columns)
M. Garcia-Sciveres, Atlas Upgrade Week 11/16/11
12
Illustration of the Power of integration
FEI4: 0.13m ATLAS Pixel ROC
~ 20mm X 20mm
Size would probably remain the
same if implemented in
65 nm
>One 32bit ARM11 processor core Per 4 columns (65LP)!
Fits in the dead area!
13
65nm: Some transistor test result
Same gate capacitance
No noise degradation at lower nodes
No thermal noise increase with radiation
No or little 1/f noise increase with radiation
M. Manghisoni et al. TWEPP 2011
14
65nm: Some radiation tolerance results
Threshold voltage
Leakage current
S. Bonacini et al. TWEPP 2011
65 nm devices seem to outperform their 130nm counterparts in their
tolerance to ionizing radiation !
15
Example 1: FEI4A (ATLAS PIXELS FOR IBL)




FEI4A
FEI3
Year
2010
2003
Technology
130nm
250nm
Chip size
20x19mm2
7.6x10.8mm2
Active area
89%
74%
Array
80x336
(26880)
18x160
(2880)
Pixel size
50x250μm2
50x400μm2
Number of
transistors
87M
3.5M
Data rate
320 Mb/s
40Mb/s
Wafer yield
65% *
80%
FEI4A 0.13u process
Performs also most of a module
Controller chip duties
Copes with higher hit rate: regional architecture and smaller pixel size
Improved cost effectiveness: Large chip with large active area
Lower power: Improved design and architecture
Increased radiation tolerance (~250Mrad)
FEI3 0.25u
process
16
FEI4 (cont’d)
• Column drain architecture (a la FEI3) saturates at high rate
– All pixel hits are sent to periphery
– Column based readout induces dead-time (during data transfer to
periphery and column readout)
• ATLAS solutions for higher rate
→ Development of regional architecture in FEI4 enabled by migration to
a finer process
17
FEI4 PIXEL REGION
• FEI4 is organized in digital regions serving 4 analog pixels
• Hits are stored locally during L1 latency
– 5 ToT memories per pixel, 5 latency counters per region
• Hits are not moved unless triggered
– only 0.25% of hits are sent to periphery
• Lower digital power consumption (6μW/pixel at IBL occupancy)
18
FEI4: Pixel front end
•
•
•
•
•
Similar design of analog pixel in FEI3/FEI4
Two-stage amplification
Clock is distributed to all digital pixel region
ToT counters within pixel digital region
ToT together with pixel address sent to periphery
FDAC
TDAC
4 Bit
FEI3
ToT
8 bit
FEI4
Vfb
+
4 bit
5 Bit
local
feedback
tune
feedbox
TDAC
7 bit
5 bit
FDAC
3 bit
4 bit
Inj0
Cinj1
Vth
local
threshold
tune
+
feedbox
Cf1
Cf2
NotKill
+
HitOut
Cc
injectIn
Preamp
Inj1
Vfb2
Amp2
-
Cinj2
19
FEI4A: A result
• FEI4 bump-bonded to planar and 3D sensors have been successfully
operated in lab test, test beams and cosmic data taking
• Tuned threshold dispersion ~30e
• FEI4 low threshold operation (~700e) shows promising results with
reasonable dispersion
• Irradiation tests with bare chips show no effect on threshold
dispersion and 20% increase in noise
103
before tuning
Constant 849
Mean
3178
Sigma
403
102
10
Threshold tuning at 1400e
1
10-1
1500 2000
2500
3000
3500
4000
after tuning
5000
Threshold [e]
Constant 2865
Mean
3100
Sigma
26
103
102
10
1
10-1
2700
2900
3100
3300
3500
Threshold [e]
20
Example 2: ATPIX65, next generation Atlas pixel readout prototype
To explore the capabilities of advanced CMOS processes to
address future HEP needs (upgrades, SLHC, )
To have a feel of what is the best way these processes
should be used to maximize ROI.
To evaluate radiation hardness (mainly SEU and new
damage mechanisms, if any!)
To keep abreast of the state of the art (if one can).
21
Pixel region (2X2) a la FEI4 if implemented in 65nm
~FEI4 AFE equivalent
Pixel size=50X100 (?)
Region logic synthesized from FEI4 verilog.
Neither 100% complete nor verified.
Just to have an idea on what is possible
22
FIE4 pixel region Vs Pix65nm region (assuming y=50u)
FEI4 2X2 REGION (100X500)
“FEI5” 2X2 REGION (100X200)
If area to be kept the same as FEI4,
about 4X more logic can be added
=> Substantial area reduction
=> Ultimately the width of a pixel will limited by practical
considerations (power distribution) and not the number of
transistors!
=> Room to add functionality
23
Snapshot of submitted pixel array
25 mm y cell pitch but 50mm bump y picth.
Power distribution will be major factor in the ultimate minimum
dimensions
Bump mask not part of the submitted layout (same size as FEI4)
24
ATPIX65A FEND BLOC DIAGRAM
Passive RC: gate
leakage limited
Inject Bloc
TDAC (+/4b tuning)
Preamp.
17fF Feeback cap.
Variable “Rff”
Single to differential+
Comparator “preamp”
Uses only 65nm Transistors
2mA to 25mA @ 1.2V
Comparator
25
ATPIX65A: Atlas Pixel prototype array
Pixels with
Added
mimcaps
(31,27,22,
18)
16 X 32 array
25m X 125m pixels
Pixels
with
Added
sensors
(row
11:31)
26
Preliminary test results
Chan 15/32 Qin: 2ke
Preamp out
Single to Diff. out
Chip found to work as expected!
VDD=1.2V
I= 5mA per pixel (can be as low as 2mA)
27
Chan 15/32 Qin: 2ke to 10ke-
Qin=10ke-; 5IFF settings
28
ATPIX65A: Noise and Threshold distribution
Channels with caps or diodes
29
ATPIX65A: ENC for some columns
Channels with
Diodes
(3 types)
....
Channels with
mimcaps
30
Fe55 spectrum as detected by one of the integrated sensors
Noise artificially Limited
2154 KeV (2.9KeV? May be partial 5.9KeV charge collection?)
For the experiment to agree with theory
(for the 5.9KeV), injection cap has to be
corrected by 15% . Still being reviewed!
5154 KeV (theory; 5.9KeV?)
1040e- pulser injection
~3.7keV. Assuming Cinj
to be nominal.
Very preliminary! Work in progress!
Chip2 high gain mode. Sensor@-8V
31
Example 3: Apsel65 65nm pixel front end with MAPS
Integrated sensor
Power consumption(mW)
ENC (e-)
Charge sensitivity(mV/fC)
Peaking time(ns)
DNW-MAPS
20
38
725
300
FFE
6
200
40
25
L. Gaioni et al. / Nuclear Instruments and Methods in Physics
Research A 650 (2011) 163–168
Fast Front End for
High resistivity pixels
32
Example 4: Fast, rad-hard CMOS direct detectors for TEM
0.35 um CMOS
TEAM2k(2009)
9.5m pixels
4Mpix, 400 f/s
0.35 um
CMOS(2009)
TEAM1k
1 Mpix
Fabrication
process
0.18 um CMOS
K2 sensor (2010)
5m pixels
16Mpix, 400 f/s
Improved radiation
tolerance
Commercial product
Pixel pitch
[µm]
Conversion
Gain
[µV/e-]
Noise
[e-]
Leakage
current
[fA]
Well
depth
[e-]
0.35 µm
9.5
9.4
30
10
90000
0.18 µm
5.0
15.5
35-40
4
23000
65 nm
2.5
21
50
8
18000
HIPPIX (2011)
65nm proto
B.Krieger, TNS 2011
33
Example 4: HIPPO, a column-Parallel CCD readout (for X-ray imaging and
muon collider applications)
column-Parallel LBNL CCD
Custom 65nm CMOS
35 e- @ 10 Mpix/s
Megapixel square sensor has ~1000 columns @ 50 μm pitch  need custom IC readout
No room for output amplifier  need charge-sensitive readout
Ultimate applications require intensive DSP  advanced CMOS process
65nm CMOS found to be the most adequate
C. Grace, TNS 2011
34
HIPPO prototype chip
16 Analog
Front ends
16 SHAs
4 ADCs
12b (80 Msps)
SERDES
(480 Mb/s)
4200 μm
HV input transistor to achieve the required noise level. Nominal transistor is too leaky!
35
HIPPO results (mixed simulation and measurements)
Preamp
ADC
Full Scale
50k /
1M e-
CCD charge
200ke-
Input noise
35 /24e-
Settling time
< 15ns
Charge loss
< 1%
Linearity
10 b
Power
5 mW
J.P. Walder,
TNS 2011
Resolution
12 b @80MHz
Noise
0.77 b
Linearity
10 b
Serial output
480 Mb/s
ADC Pitch
200 μm
ADC Area
0.35 mm2
Power per ADC
30 mW
36
50 μm
ATLAS 3D EFFORT
FE-I3 CMOS 250 nm
400 μm
FE-I4 CMOS 130 nm
125 μm
FE-TC4 CMOS 130 nm 2 layers
M6
M6
Bond Interface
< 50 μm
M5
M4
M3
M2
M1
< 100 μm
Super Contact
FE-X5-3D CMOS xx nm 3 layers
Achieves integration vertically
Optimized “tiers”
One of the “more than Moore” ways
Many challenges!
A.Rozanov Atlas Upgrade Week 11/16/11
Tezzaron/chartered 2 tier Example
M1
M2
M3
M4
M5
Tier 1
(thinned wafer)
Super Contact
50 μm
250 μm
Back Side Metal
Tier 2
50 μm
sensor
37
Conclusions
Unprecedented advances in IC technology are offering new ways to implement readout
systems (for all kind of detector systems).
New challenges seem to be more addressable with scaled down technologies.
Future systems will require smaller geometries, lower power, higher level of
processing, high radiation tolerance, lower cost per function, …etc
Among the advantages of newer technologies are:
Very high integration density
Inherent high radiation tolerance
A reasonable number of device types for extra design flexibility
Availability of high quality passives
A high number of metal levels
Skewing the mix of functional blocs towards digital would result in a better area usage
and chip yield. Not to mention flexibility (programmability) and Productivity (think
advanced digital tools)
A myriad of challenges related to ultra complex processes and ultra small devices are
associated with these technologies. For some of these, mitigation techniques are readily
available
A unique challenge to the research community is perhaps the cost of these advanced
processes (given the low volume usually involved). Common wisdom applies: for some
applications plain old technologies would remain the optimal choice.
38
Acknowledgements
Many Thanks to all people whose work has been mentioned and to my
colleagues at LBNL For their help.
Please refer to the referenced work for more exciting details.
39
Backup slides
40
ATPIX65: ENC Vs Diode bias
41
ATPIX65: ENC Vs Preamp Bias
42
ATPIX65: ENC Vs IFF (feedback current)
43
ATPIX65: Threshold Vs Preamp current
44
ATPIX65: Threshold Vs feedback current
45
Timewalk @Preamp current of 2ma and 0.2mA
46
ATPIX65: Fe55 spectrum as detected by one of the integrated
sensors
?
?
(V)
Very preliminary! Work in progress!
Chip2 high gain mode. Sensor@0V
47
http://spie.org/x20060.xml?ArticleID=x20060
Lower part of the Am241 spectrum as detected by one of the
integrated sensors
?
?
Chip1 low gain mode
(V)
Very preliminary! Work in progress! Low statistics
48