Transcript deep N-well (DNW) MAPS

P-ILC
Stato delle cose
 caratterizzazione del prototipo in 130 nm (Pv, Mi)
Sblocco s.j. 50 + 3 kEUR (produzione chip + scheda digital I/O V1495 CAEN)
 EUDET (Fe, Mi)
 attivita’ sui SiPM (Roma I & LNF)
 Attivita’ a Lecce
 programma 2009
Massimo Caccia
Riunione CSN1
Ferrara, 19 Maggio 2008
Deep n-well MAPS concept
PMOS
NMOS
P-well
Buried N-type
layer
Deep N-well
structure
Standard N-well
P-epitaxial
layer
P-substrate
In triple-well CMOS processes a
deep N-well is used to isolate Nchannel MOSFETs from substrate
noise
Such features were exploited in
the development of deep N-well
(DNW) MAPS devices
A DNW is used to collect the charge released in the epitaxial layer
A readout channel for capacitive detectors is used for Q-V
conversion  gain decoupled from electrode capacitance
NMOS devices of the analog section are built in the deep N-well
Using a large detector area, PMOS devices may be included in the
front-end design; of course the of the DNW area to the area of all the Nwells (deep and standard) matters…
ILC DNW MAPS demonstrator
A 16x16 MAPS demonstrator chip has been designed in the 130 nm bulk CMOS
technology by STM
Further pitch reduction might be
achieved by:
replacing the digital time stamp register
with an analog one
using a further scaled process, namely a
90 nm CMOS technology by STM,
supposed to have substrate features
similar to those of the 130 nm process
•Preamplifier
•Discriminator
Sparsification
logic
•Token passing
DNWcore
Time stamp
•Hit-latch
sensor
register
•Bus control FF
•Nand gate
25 mm
25 mm
Increase in the number of
elements just requires larger Xand Y-registers and serializer
There is more than one structure on the chip…
M1
16 x 16 pixels
Full digital machine
Binary output
M2
8 x 8 pixels
Full digital machine
Analog output of a selected
pixel
M3
3 x 3 pixels
NO digital machine
Analog output of all of the pixels
 design submitted in November 06
 delivery expected in April 07
 actually made available in July 07 (10 [15] chips with 100 [250] mm thickness)
 January  May 2008 CHARACTERIZED
SDR0 chip and test board
Test board designed by Marcin Jastrzab
University of Science and Technology, Cracow
(Poland) and University of Insubria, Como (Italy)
Credit: Fabio Risigo University
of Insubria, Como (Italy)
SDR0 experimental results
Preamplifier response
to an external calibration signal
Average charge sensitivity  0.7 V/fC
ENC = 40 e rms @ CD=120 fF
(preamplifier input device: ID = 1 mA,
W/L = 22/0.25)
Threshold dispersion  60 e
y = m2 * M0
(in 16x16 matrix and 8x8 matrix)
Value
Error
763,63 6,7819
m2
Chisq
R
158,53
0,99786
NA
NA
No crosstalk between pixels,
no correlated noise
Pixel output signal vs injected charge
0,12
140
preamplifier output [mV]
preamplifier output [mV]
160
1 MIP cluster
signal
120
100
80
60
40
Pixel 2_2
Charge sens. = 731 mV/fC
20
0
0
0,05
0,1
Qinj [fC]
0,15
0,2
0,1
central pixel response
to injected charge
0,08
0,06
0,04
other 8 pixels
in the 3x3 matrix
0,02
0
-0,02
-5
0
5
10
t [ms]
15
20
SDR0 experimental results
3x3 matrix response to 55Fe source
55Fe
data
confirm pixel
gain
calibration
Test con sorgente laser
Caratterizzazione sperimentale dei dispositivi MAPS
Proprietà del substrato in termini di carica raccolta e sharing di carica tra pixel
Strumentazione impiegata
Laser LD-1060 Fabry-Peròt (FP)
Focalizzatore in fibra ottica – spot 20
µm
Accoppiatore 1x3 singlemode
1060nm
Newport universal motion
controller/driver modello ESP300
Oscilloscopio DSO LeCroy WaveRunner
64Xi
Generatore di forme d’onda Agilent
33250A
SDR0 experimental results
3x3 matrix response to infrared laser
0,08
preamplifier output [V]
0,07
central pixel response
to injected charge
0,06
2_2
0,05
2_1
0,04
2_3
3_1
0,03
other 8 pixels
in the 3x3 matrix
0,02
1_3
1_2
3_2
1_1
0,01
3_3
0
0
5
10
Time [ms]
15
20
SDR0 experimental results
matrix scan with infrared laser
Total collected charge in
a 5x5 cluster as a function
of laser position
matrix scan with infrared laser:
charge collected in pixels
 and total charge collection
SDR0 experimental results
Digital readout: pixel address
(8x8 matrix)
Digital readout: threshold scan (16x16 matrix)
1 hit pixel (focused laser on the central pixel)
Threshold dispersion 60 e
 Plateau at 1 pixel
Moving on
There is a very elegant solution to the problem of reducing pixel
pitch and at the same time increasing pixel functionalities and fill
factor….
…. and it can be done at lower cost with respect to the 130nm
CMOS technology accessed through the CMP broker…. (~50K
Euro vs ~80K Euro)
… it can be done both preserving the present device architecture
and introducing a very promising (also for other applications)
technology implementation
Scenario of microelectronics processes and performance typically
changes in a time scale of 1-2 years.
3D vertical integration based on DNW MAPS
(conceptual)
Use vertical integration
technology to interconnect two
130nm CMOS layers
(R. Yarema)
Handle for CMOS
Mostly digital CMOS tier
PMOS
Standard CMOS
NMOS
Tier interconnection and vias with
industrial technique
Analog and DNW sensor CMOS
(mostly NMOS) tier
NMOS
PMOS
P-well
Buried N-type
layer
Deep N-well
structure
Standard N-well
P-substrate
Submission of 2-tier MAPS
The 2-tier MAPS approach is possible in the TezzaronChartered process, sharing the costs with Fermilab and
IN2P3.
Chartered Semiconductor (Singapore) is one of the main
silicon foundries in the world.
Tezzaron Semiconductor (Singapore) is specialized in the
vertical integration of CMOS layers.
An engineering run (25 8-inch wafers) in the 130nm CMOS
will be done at Chartered Semiconductor.
Tezzaron will perform the 3D assembly of the 130nm CMOS
wafers. Very high yield is expected.
3D Multi-Project Run
• We have been invited by Fermilab (Ray Yarema) to join a 3D multi
project run using Tezzaron-Chartered.
• The run is scheduled in December ’08 – (not later than) January ‘09
• There will be only 2 layers of electronics fabricated in the Chartered 130
nm process, using only one set of masks.
This process has a very similar resistivity as the 130nm STMicroelectronics
process. It is very reasonable to expect very similar charge collection
properties.
• The wafers will be bonded face to face by Tezzaron.
Typical frame
AB
AB
Flip
Horz.
Thin backside
of top wafer, use
circuit B only
Top Wafer
AB
AB
AB
AB
Bottom Wafer
Note: top and bottom wafers are identical.
On bottom
wafer, use
circuit A only
Make contact to
backside of
metal on B circuits.
Face to Face Bonding
Reticle size
24 x 32 mm2
Chip 1 (E2-E1):
Matrice 256x256 “ILC class”, pitch ≤ 20 mm, versione 3D
Chip 2 (F2-F1):
• Matrice 128x128 “ILC class”, versione 2D
• Matrici di test con architetture di readout alternative APSEL,
DIGIMAPS(compatibili con utilizzo sia in ILC sia in SuperB)
[on DIGIMAPS (Roma 3; E. Spiriti): on pixel sparsification, analog output, no deep
n-well based  charge diffusion & clustering; currently 130 nm design,
nmos only under test]
EUDET
To-do list:
 read out of
the MIMOSA18
(512 x 512, 10 um)
 VME cycle
optimization to
increase the
event rate
 design the
daughter boards
for the M22+ (full
digital)
 complete the
sparsification by
clustering (Milano)
SiPM - Roma 1
DCR & cross talk
MePhi
Entries
Entries
ξ cross talk probability
Ptg  1 
N0
 1.2
N1
Getting ready for the
Temperature dependence
and
Photon Detection Efficiency Measurement
The new dark and electrically shielded box for SiPM and for reference
Photo-detector
Cosmics, Spring 08 (LNF)
coincidence of
2 trigger counters
RPC tracker,
6 x-y chambers
3 MPPC counters
Temperature sensor
100-150 evts/day with x-y tracking on the 3x3cm2 tiles
• Investigation of SensL SiPMs 1300px, reading a BC-408
tile of 3mm thickness
• Comparison Ham400,3mm e Ham400,6mm
• Much worse S/N for SensL
Next steps
• Cosmic data
taking ongoing
• BTF test in June
• Complete
program by
Dec.2008
Activities in Lecce
