Transcript Lifetime_FEE2014x

LAr TPC Electronics CMOS Lifetime at 300K and 77K
Shaorui Li, Jie Ma, Gianluigi De Geronimo, Hucheng Chen, and Veljko Radeka
Brookhaven National Laboratory, NY, USA
Outline:
1. Overview of basics on hot-carrier effects and lifetime.
2. CMOS Lifetime due to aging in TSMC 180nm:
A. CMOS lifetime in dc operation: analog front-end ASIC ;
B. CMOS lifetime ac operation: logic circuits and FPGAs.
3. Thermal Cycling
4. Future R&D Needs: Commercial FPGA and regulators
1
Introduction
• Motivation: Low noise multiplexed readout of noble liquid
detectors for neutrinos, nucleon decay, dark matter, double beta
decay, in particular for very large liquid argon Time Projection
Chambers (TPCs).
•The goal: A continuous and unattended cryogenic operation
for a long time (>10-20 years).
• Electronics for noble liquid TPCs: It is known that CMOS
operation at cryogenic temperature (~-200C) offers considerable
advantages as compared to room temperature operation, with
respect to speed, transconductance/drain current ratio
(subthreshold slope) and noise.
•The key question: How is the lifetime of CMOS affected by
cryogenic operation?
2
Static Characteristics: Lower Power at 77K
MEASURED
120
Favorable for cryogenic
operation:
NMOS PMOS T=77K
100
• higher gm -> lower noise
L=360nm
L=270nm
-1
g m /I D [V ]
• higher gm/ID -> lower power
L=180nm
80
60
NMOS PMOS T=300K
L=360nm
L=270nm
40
L=180nm
20
CMOS018
0
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
Drain Current Density [mA/mm]
Asymptotic value at weak inversion:
~ 30 at T  300K
gm
q


ID
nk BT ~ 116 at T  77K
Design region (approx.)
for low power and low
noise at 77K (moderate
inversion): gm increase
by a factor of ~2.
3
CMOS Lifetime Introduction
at Cryogenic Temperatures
• Most failure mechanisms (e.g. electromigration, stress migration, timedependent dielectric breakdown, and thermal cycling) are strongly temperature
dependent and become negligible at cryogenic temperature.
•The only remaining mechanism that may affect the lifetime of CMOS devices at
cryogenic temperature is the degradation (aging) due to channel hot carrier
effects (HCE).
• The degradation mainly concerns NMOS devices - PMOS usually exhibits a
lifetime much longer than NMOS.
• Lifetime due to HCE aging: A limit defined by a chosen level of monotonic
degradation in e.g., drain current, transconductance. The device “fails” if a
chosen parameter gets out of the specified circuit design range. This aging
mechanism does not result in sudden device failure.
• The lifetime due to HCE at both the cryogenic temperature, as well as at room
temperature, is limited by a predictable and a very gradual degradation (aging)
mechanism which can be controlled or avoided by device design and operating
conditions. In this study we have been following the basics established in the
literature, e.g., Hu et al. (1985), and the practices adopted more recently by
4
Chen&Cressler et al. (2006), as well as by industry.
Overview of Basics on Hot-Electron Effects and NMOS Lifetime
• Some hot electrons exceed the energy required to create an
electron-hole pair, i  1.3eV , resulting in impact ionization. Electrons
proceed to the drain. The holes drift to the substrate. The substrate
current,
I sub  C1 I ds e i q Em
(1)
• A very small fraction of hot electrons exceeds the energy required
to create an interface state (e.g., an acceptor-like trap), in the SiSiO2 interface, it  3.7eV , for electrons (~4.6eV for holes). This
causes a change in the transistor characteristics (transconductance,
threshold, intrinsic gain). The time required to change any important
parameter (the changes in different parameters are correlated) by a
specified amount (e.g., gm by -10%) is defined as the device
lifetime. It can be calculated as,
  C2
W it
e
I ds
q Em
(2)
q = electron charge
λ=electron mean free path
Em= electric field Em  Vds  Vdsat
Ids= drain-source current
W= channel width
C1, C2 - constants
• It has been widely recognized that Isub is a monitor for all hot-electron effects and it is the best predictor of
device lifetime, because both observable hot electron effects (electrical and optical) are driven by a common
driving force –the maximum channel electric field Em , which occurs at the drain end of the channel.
• The substrate current is connected to the lifetime (defined by any arbitrary but consistent criterion) by
 I ds W 
1
 I sub
I ds 
a
(3)
a
it
i
~ 2.9  3.2
i ~ 1.3eV ;it ~ 3.7eV  4.1eV
5
Basics of Hot Carrier Effects
• Degradation is due to impact ionization:
→ shift in Vth and gm
• Substrate current is a monitor of impact ionization
• increases steeply with drain voltage
•has a broad maximum at VGS ≈ VDS/2
• Commercial technologies are rated > 10 years lifetime (10% gm shift) at
T = 300 K, L = Lmin, VDS = nominal VDD+5%, VGS ≈ VDS/2
• A lower temperature results in increased mean free path λ increasing the
substrate current Isub and gm degradation. Degradation is independent of
temperature if the product λ(VDS – VSAT) is kept constant.
• Accelerated lifetime test (well-established by foundries): transistor is placed
under a severe electric filed stress (large VDS), to reduce the lifetime due to hotelectron degradation to a practically observable range, by a drain source voltage
considerably higher (~80%) than the nominal voltage (1.8V for Lmin=180nm).
6
Stress Test Flow Chart and Layout of test NMOS transistors
2µm
Test transistors, NMOS L=180nm, W=10µm (5 fingers x
2µm), designed to have negligible IR drop and power
dissipation <15mW in stress tests to prevent
temperature change due to self-heating.
gm degradation [%]
100
Vds=3.2V,77K
Vds=2.8V, 77K
Vds=3V,77K
Vds=2.8V, RT
Vds=3V,RT
Vds=3.2V,RT
10
1
1
10
2
10
3
10
4
10
Stress time [s]
5
10
7
6
10
CMOS in dc Operation: Analog Front-End ASIC
Measurement Type I:
10
“Stress Plot”
3
 I ds W 
Vds=2.8V
2
 I sub
I ds 
1E9
a
Lifetime ~ 3200 yrs at Vds=1.8V, 77K
1E7
300K Slope ~3.10
10
Vds=3.1V
Vds=2.8V
Vds=3.2V
10
0
300K
100000
Vds=3.0V
1
77K
1000
10
1E-3
Vds<1.8V
3.2, 3.1, 3.0, 2.8 V
Vds=3.2V
-1
10
ASIC design:
Vds<1.5V
0.1
Vds=3.0V
77K Slope ~2.94
10
1.8V 1.7V
1
*IDS/W (s*A/m)
*Ids/W [s*A/m]
10
it
1
 I 
ln  ds  

Vds  Vdsat
 W  qEm
1E-5
-2
10
-1
10
0
0.1
0.2
0.3
0.4
0.5
0.6
-1
Isub/Id
1/VDS(V )
• The measured points at both 300K and 77K are very close to the characteristic
slope for the interface state generation, a   it  i  3
• The projected lifetime at 300K is ~ an order of magnitude longer than at 77K.
Reducing Vds at 77K by ~ 6% makes the lifetime equal to that at 300K. Design at
low Ids/W for even longer lifetime.
8
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
1E-8
NMOS L=180nm, W=10µm (5x2µm), Vgs=1V
Stressed lifetime=798s at Vds=3.2V, 77K
1E-10
Stressed lifetime=8506s at Vds=3.2V, 300K
10
-10
10
-11
10
-12
10
-13
10
-14
L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm
L=360 nm;
-”- ; Ids/W=1.0µA/µm
L=9 µm
L=270 nm
L=9 µm
1E-9
1E-11
Lifetime ~ 5500 yrs at Vds=1.8V, 77K
3
  I sub
1E-12
Isub/W (A/m)
Isub/W [A/m]
Measurement Type II: Substrate Current Density Isub /W vs 1/Vds
300K
77K
1
Vds=1.8V
1/Vds [1/V]
1E-14
1E-15
1E-16
1E-17
ASIC design:
Vds<1.5V
0
1E-13
1E-18
1E-19
2
1E-20
0
2
1.5V 1.0V
0.5V
4
6
1/Vds (1/V)
• One order of magnitude in substrate current Isub corresponds to three orders
of magnitude in lifetime. At 77 K, Vds = 1.8 V projects a lifetime of ~5500 years.
• Isub/W and 1/Vds distribution for all transistors in the analog front-end ASIC for LAr
TPC (TSMC 180nm, 1.8V node) shows that all transistors are well below nominal
voltage of 1.8V and at low Isub; Reduced Vds < 1.5 V results in essentially making
HCE negligible and a very long extrapolated life time.
9
10
NMOS L=180nm, W=10µm (5x2µm)
-4
10
-5
10
-6
10
-7
10
-8
10
-9
pre stress
post stress
6000 s -> 10% gm degradation
300 K
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
Equivalent input noise [V/sqrt(Hz)]
Equivalent input noise [V/sqrt(Hz)]
Noise Degradation: Less Degradation in PMOS
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
PMOS L=180nm, W=10µm (5x2µm)
pre stress
post stress
12960 s -> 2% gm degradation
300 K
1
10
2
10
3
10
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
pre stress
post stress
920 s -> 10% gm degradation
post stress
3900 s -> 15% gm degradation
77 K
10
1
10
2
10
3
10
4
10
5
Frequency [Hz]
4
10
5
10
6
10
7
Frequency [Hz]
10
10
6
10
7
10
8
Equivalent input nosie [V/sqrt(Hz)]
Equivalent Input noise [V/sqrt(Hz)]
Frequency [Hz]
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
pre stress
post stress
1500s stress -> 2% degradation of gm
post stress
5000s stress -> 3.5% degradation of gm
77 K
10
1
10
2
10
3
10
4
10
5
10
6
10
7
Frequency [Hz]
• PMOS: much less degradation than NMOS
• PMOS is used in the preamp input and, by design, it is the main noise
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contributor in the front-end ASIC.
CMOS Lifetime in AC Operation: Logic Circuits and FPGAs
• Long established (e.g. Quader&Hu et al.(1994), White&Bernstein (2006)] and
adapted by foundries: considering the ac stress as a series of short dc stresses,
each for effective stress time teff during the switching cycle, strung together.
• The lifetime of digital circuits (ac operation) is extended by the inverse duty
factor 1/(fck teff ) compared to dc operation. This factor is large (>100) for deep
submicron technology and clock frequencies (up to 200 MHz) which may be
needed for the TPC readout.
• Design guidelines for digital circuits and FPGAs: Keep the inverse duty factor
1/(fck teff ) high . Additionally, reducing Vds by 10% adds an order of magnitude
margin to the lifetime.
• Rough estimation of teff [Quader&Hu et al. (1994)]:
-1/4 of the gate voltage rise time for NMOS
-1/10 of the gate fall time for PMOS
More detailed estimation can be found in the design
manuals of major foundries. An accurate estimation
requires a calculation of the substrate current during
the change of state.
Quader&Hu et al. (1994)
11
Thermal Cycling of FE ASICs and FE Boards (for MicroBooNE)
Cold motherboard with 12 ASICs populated. During extensive testing of ASICs
and the motherboard, ASICs have gone through ~2200 immersions (of multiple
chips) in LN2, the board has been immersed ~40 times without a single failure.
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Future R&D Needs: Commercial FPGA and Regulators
• FPGA candidates for cryogenic operation:
Vendor
Family
Technology
Speed
of GTX
[Gbps]
# of GTX
Memory
[Mbit]
Core
Voltage
[V]
Status
Altera
Arria GX
90 nm
3.125
4-12
1.2-4.5
1.2
Tested by BNL
Altera
Arria II
40 nm
6.375
8-24
2.9-16.4
0.9
Tested by BNL
Altera
Stratix II GX
90 nm
6.375
4-20
1.4-6.7
1.2
Tested by SMU
Altera
Cyclone IV E
60 nm
n/a
n/a
0.3-3.9
1.0, 1.2
Tested by BNL
Altera
Cyclone IV GX
60 nm
3.125
2-8
0.5-6.5
1.2
Tested at BNL
Altera
Cyclone V
60 nm
3.125
2-8
0.5-6.5
1.2
Tested by BNL
Xilinx
Virtex 5
65 nm
6.5
0-24
0.9-18.6
1.0
Tested by BNL
✔
✗
✔
✔
✔
✗
✗
List of FPGA screening tests: configuration (JTAG & Active Serial), embedded memory, high speed
transceiver, I/O interface.
• FPGA Lifetime: a standard method is to observe ring oscillator frequency under severe Vds
stress [Wang et al. 2006], as degradation of Ids leads to increased rise (propagation) time and
reduced ring oscillator frequency. Needs further R&D.
• Regulators for cryogenic operation: 1.2 V and 2.5 V for FPGA, and 1.8 V for LAr ASICs.
Selected 3 baseline devices, Globaltech GS2915L18F, TI TPS74201/74401, from a total of 19
devices (from ADI, Intersil, Linear, Maxim, National) tested.
Cold longtime experiment: Globaltech GS2915L18F tested >2 years; TI TPS74201/74401 will
start soon. Needs further R&D on lifetime.
13
Principal Findings and Design Guidelines
1.1. Two different measurements were used: accelerated lifetime measurement
under severe electric field stress by the drain-source voltage (Vds), and a
separate measurement of the substrate current (Isub) as a function of 1/Vds.
The former verifies the canonical very steep slope of the inverse relation
-3
between the lifetime and the substrate current , τ  I sub , and the latter
confirms that below a certain value of Vds a lifetime margin of several orders of
magnitude can be achieved for the cold electronics TPC readout.
1.2. Lifetime of digital circuits (ac operation) is extended by the inverse duty factor
1/(fck teff ), compared to dc operation. This factor is large (>100) for deep
submicron technology and clock frequency needed for TPC. As an additional
margin, Vds may be reduced by ~10%.
2. PC boards, packages, hybrids: Extremely low failure rate (incidence) in ATLAS
LAr and NA48 LKr calorimeters, over a long time scale demonstrates on a
large scale that surface mount circuit board technology withstands very well
even multiple abrupt immersions in LN2 applied in board testing, and that the
total failure incidence in continuous operation over time, ranging from 6 to13
years so far, is very low.
14
References (only a few key references, among numerous references on
the subject, are given here):
1.
2.
3.
4.
5.
6.
7.
8.
S. Li, J. Ma, G. De Geronimo, H. Chen, and V. Radeka, “LAr TPC electronics CMOS lifetime
at 300 K and 77 K and reliability under thermal cycling,” IEEE Trans. Nuclear Science, vol.
60, no. 6, pp. 4737-4743, Dec. 2013.
G. De Geronimo, A. D’Andragora, S. Li, N. Nambiar, S. Rescia, E. Vernon, H. Chen, F.
Lanni, D. Makowiecki, V. Radeka, C. Thorn, and B. Yu, “Front-end ASIC for a liquid argon
TPC,” IEEE Trans. Nuclear Science, vol. 58, no. 3, pp. 1376-1385, June 2011.
J. R. Hoff, R. Aroar, J. D. Cressler, G. W. Deptuch, P. Gui, N. E. Lourenco, G. Wu, and R. J.
Yarema, “Lifetime studies of 130 nm nMOS transisors intended for long-duration, cryogenic
high-energy physics experiments,” IEEE Trans. Nuclear Science, vol. 59, no. 4, pp. 17571766, Aug. 2012.
C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot-electron-induced
MOSFET degradation-model, monitor, and improvement”, IEEE Journal of Solid-State
Circuits, vol. sc-20, no. 1, pp. 295-305, Feb. 1985.
T. Chen, C. Zhu, L. Najafizadeh, B. Jun, A. Ahmed, R. Diestelhorst, G. Espinel, and J. D.
Cressler, “CMOS reliability issues for emerging cryogenic Lunar electronics applications,”
Solid-State Electronics, vol. 50, pp. 959-963, 2006.
V.-H. Chan and J. E. Chung, “Two-stage hot-carrier degradation and its impact on
submicron LDD NMOSFET lifetime prediction”, IEEE Tran. Electron Devices, vol. 42, no. 5,
pp. 957-962, May 1995.
K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET’s”,
IEEE Tran. Electron Devices, vol. ed-30, no. 8, pp. 871-876, Aug. 1983.
P. K. Hurley, E. Sheehan, S. Moran, and A. Mathewson, “The impact of oxide degradation
on the low frequency (1/f) noise behavior of p channel MOSFETs”, Microelectronics
Reliability, vol. 36, no. 11/12, pp. 1679-1682, laar, “Hot-Ca1996.
15
9. K. N. Quader, E. R. Minami, W.-J. Huang, P. K. Ko, and C. Hu, “Hot-Carrier-Reliability Design
Guidelines for CMOS Logic Circuits”, IEEE Journal of Solid-State Circuits, vol. sc-29, no. 3, pp.
253-262, March 1994.
10. J. Wang, E. Olthof, and W. Metserrier Degradation Analysis Based on Ring Oscillators”,
Microelectronics Reliability, 46, pp. 1858-1863, 2006.
11. M. White and J.B. Bernstein, “Microelectronics Reliability: Physics-of -Failure Based Modeling
and Lifetime Evaluation”, JPL Publication 08-5 2/08.
Note: Manuals for each CMOS technology node provided by major foundries (e.g.
IBM) are devoted to guidelines how to maximize transistor lifetime.
16
Backup Slides
17
Static Characteristics: Larger Sub-Threshold Slope at 77 K
10
10
SIMULATED (foundry parameters)
LN
RT
8
6
CMOS018
MEASURED
LN
RT
8
ID [mA]
ID [mA]
ID vs VDS
CMOS018
6
4
4
2
2
NMOS, L=0.18µm, W=10µm
0
0.0
0.3
0.6
0.9
1.2
1.5
NMOS, L=0.18µm, W=10µm
0
0.0
1.8
0.3
0.6
VDS [V]
1
CMOS018
CMOS018
gm
0
1.8
gm
0
10
ID
)
0)nV
( ln(1
MEASURED
LN
RT
-3
10
mV/
dec
10
~18mV/dec
~72
-4
-2
~72
I D [mA], g
(foundry parameters)
LN
RT
10
10
m
SIMULATED
~18mV/dec
-3
mV/
dec
10
[mS]
( ln(1
m
-2
10
-1
0)nV
10
ID
T
)
T
-1
[mS]
1.5
10
10
I D [mA], g
1.2
1
10
ID vs VGS
0.9
VDS [V]
-4
10
NMOS, L=0.18µm, W=10µm
NMOS, L=0.18µm, W=10µm
-5
-5
10
0.0
10
0.3
0.6
0.9
VGS [V]
1.2
1.5
1.8
0.0
0.3
0.6
0.9
VGS [V]
1.2
1.5
1.8
18
Some differences in saturation voltage, sub-threshold slope, transconductance
Noise: Lower White Noise and Lower PMOS 1/f Noise at 77K
T = 300K
3
10
L=180nm, W=1mm (20µm x 50)
VDS=400mV, T=300K
Input noise spectral density [nV/Hz]
Input noise spectral density [nV/Hz]
10
2
10
1/f
NMOS
ID=3.2mA (IC=1)
1
10
PMOS
ID=0.7mA (IC=1)
fit curve
0
10
white
1/f

CMOS018
-1
10
T = 77K
3
1
10
2
10
L=180nm, W=1mm (20µm x 50)
VDS=400mV, T=77K
2
10
1/f
NMOS
ID=3.2mA (IC=3)
1
10
PMOS
ID=0.7mA (IC=0.3)
fit curve
0
10
white
1/f
CMOS018
-1
3
10
4
10
5
10
6
10
7
10
Frequency [Hz]
• comparable 1/f noise amplitude
(i.e. comparable noise at 1 Hz)
• different 1/f noise slope:
PMOS > NMOS
-> PMOS more advantageous for
low-noise application.
8
10
10

1
10
2
10
3
10
4
10
5
10
6
10
7
10
Frequency [Hz]
• lower white noise than at 300K
• NMOS
• comparable 1/f noise amplitude
• Lorentzian packet
• PMOS
• lower 1/f noise amplitude 19
• 1/f noise slope < 1
8
10
Input MOSFET Optimization for LAr TPC Analog Front-End ASIC
1200
N036
1100
Design input PMOSFET
for 200pF detector
electrodes (wires)!
ENC [rms electrons]
1000
P018
900
P027
800
P018
700
P036
300K
77K
600
500
CDET=200pF
400
PK=1s
P027sim
P027
ID=2mA
300
1
10
100
Gate Width [mm]
Selected size and operating point:
original (simul. noise) vs. revised (meas. noise)
• ID = 2 mA (3.6 mW)
• W/L = 10 mm / 270 nm
• IC 300K ≈ 0.4 0.3
• gm_300K ≈ 45 mS 48 mS
• Cg_300K ≈ 14 pF 25 pF
20 mm / 270 nm
IC 77K = 1.25 1
gm_77K = 90 mS 118mS
Cg_77K = 18 pF 28 pF
1000
An improvement of ENC
(~530 e- to ~420 e-) achieved
using measured noise
parameters.
20
Lifetime vs 1/Vds extracted from the stress measurements
10
16
Both NMOS and PMOS Have Same Size: W=10um(52um), L=180nm
15
PMOS, RT, 2% deg of gm
NMOS, RT, 10% deg of gm
NMOS, 77K, 10% deg of gm
10
14
10
13
1.7 x 107 yrs
8.9 x 104 yrs
10
12
10
Lifetime [s]
11
10
10
10
9
10
5300 yrs
8
10
7
10
6
10
5
10
4
10
3
10
10
Vds=1.8V
2
0.30
0.35
0.40
0.45
0.50
0.55
0.60
1/Vds[1/V]
PMOS shows ~2 orders of magnitude longer lifetime than NMOS.
21