Transcript imecas

Comparison Study of Bulk and SOI
CMOS Technologies based Rad-hard
ADCs in Space
Feitao Qi , Tao Liu , Hainan Liu , Chuanbin Zeng , Bo Li , Fazhan Zhao , Jiantou Gao , Gang Zhang , Jiajun
Luo , Zhengsheng Han , and Zhongli Liu
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA
Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences, Beijing 100029, CHINA
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Overview
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• INTRODUCTION
• SYSTEM ARCHITECTURE
• CIRCUITS DESIGN
• HARDENED APPROACHES
• EXPERIMENTAL RESULTS
• CONCLUSION
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INTRODUCTION
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Harsh Space Environment:
 Earth's radiation belts
Reliability
of ADC
 Cosmic rays
Solar proton events
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INTRODUCTION
N+
P-
P+
N+
N-
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P+
N+
P+
P+
N+
SiO2
NP-
Si
Si
(a)SOI CMOS
(b) Bulk CMOS
Rad-hard SOI CMOS V.S. Bulk CMOS :

higher speed
 lower parasitic capacitance
 smaller short channel effects
Rad-hard SOI
CMOS technology
is more suitable
for space
applications
 excellent capability of radiation hardness
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INTRODUCTION
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RHBD & RHBP
Radiation Hardened by Design and Radiation Hardened by Process
A 10bits 25Msps high reliability pipelined ADC as a prototype
ADC
1992
Integrating analog to digital converter radiation hardness
test technique and results
2006
Single-Event Sensitivity and Hardening of a Pipelined Analog-to-Digital
Converter
2013
Radiation-Tolerant Code-Density Calibration of Nyquist-Rate Analog-to-Digital
Converters
2002
Comparison of the sensitivity to heavy ions of 0.25-μm
bulk and SOI technologies
transistor
level
2013 Performance Comparison Between Bulk and SOI Junctionless Transistors
comparison
2014 Comparison of analog performance between SOI and Bulk pFinFET
circuit level This Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADCs
comparison work
in Space
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INTRODUCTION
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• The bulk and SOI based CMOS ADC have identical schematic design and
layout floor plan
•The bulk CMOS technology and radiation hardened SOI CMOS technology
have identical technology node
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SYSTEM ARCHITECTURE
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 Sample and Hold Front-end
 Extend the input bandwidth
 3+3+3+4 structure
 2.5bits/stage for first three stages
 4bits/stage for last stage
 Digital Correction Logic
 Correct the error from comparators within the system redundancy
VINP
SHA
VINN
MDAC1
GAIN=4
3
A/D
3
MDAC2
GAIN=4
3
A/D
3
MDAC3
GAIN=4
3
A/D
3
A/D
4
DIGITAL CORRECTION LOGIC
OUTPUT BUFFERS
10 BITS
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CIRCUITS DESIGN
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 Sample and Hold Circuit
Φ2
+
OPAMP
SW1
 better radiation hardness capability
• Larger feedback factor
CS
Φ1P
VINP
VINN
SW2
Φ1
SW4
VCM
Φ1P
 lower power consumption
Φ1
SW3
 capacitor flip-around architecture
CS
+
VOP
VON
-
• lower load capacitor
Φ2
 bottom plate sampling and
bootstrapped switch
 reduce the nonlinear effects of the
switch
• charge injection
• clock feed through
 improve the input bandwidth
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CIRCUITS DESIGN
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 Sample and Hold Circuit
+
-
VO
VIN
-
-
+
• DC offset increasing
+
• gain and bandwidth reduction
-
 Effects of opamp caused by TID
+
-
amplifier
+
+
-
 gain-boosted folded cascade
 efficiently improve the gain without
reducing the bandwidth
 Switched Capacitor Comparator with
Φ2
Φ2P
Φ1
+
VREFP
VINP
a preamplifier
VINN
 Low DC offset
 wide input common mode range
Φ1
-
Φ2
Φ2P
VREFN
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PREAMP
 Switched Capacitor Comparator
Φ1PN
+
+
+
-
VOP
VON
-
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RADIATION HARDENED APPROACHES
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 Hardened System and Circuits for ADC prototype
Properly determine and design system
structure and circuits
the 2.5bits/stage system structure
the capacitor flip-around S/H
the gain-boosted folded cascade amplifier
 the switched capacitor comparator with a
preamplifier
Properly increase the current and capacitor
value in sensitive parts
generates much smaller deviations when radiated
deviations from comparators will be corrected by
the digital error correction logic
 Hardened Layout for Bulk ADC
Mitigate the sensitivity of Single event
Latch-up
Enough substrate contact around the transistor
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RADIATION HARDENED APPROACHES
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 Radiation Hardened SOI CMOS Technology
Single event Latch-up Immunity
N+
P-
N+
P+
Join silicon dioxide on silicon
SiO2
substrate
Si
N-
P+
SEU and SEFI sensitivity mitigation
Smaller charge collection volume
 Other Radiation Hardened Measures
High level total ionizing dose radiation
hardened
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EXPERIMENTAL RESULTS
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 Electrical Experiment
Table 1 Electrical Characteristics Comparison
of SOI-based ADC and bulk CMOS ADC
SOI ADC
（a）SOI CMOS ADC
（b）Bulk CMOS ADC
Bulk ADC
FS(Hz)
25M
Freq_vin(Hz)
2M
5
Supply（V）
240
Consumption（mw）
DNL(LSB)
±0.4
±0.4
INL(LSB)
±0.5
±0.5
SNR(dB)
60.5
59.6
SFDR(dB)
72.3
74.4
SINAD(dB)
60.2
59.2
ENOB(bits)
9.7
9.5
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EXPERIMENTAL RESULTS
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FFT PLOT
0
 Electrical Experiment
characteristic
smaller parasitic capacitance
better I-V characteristic
-40
AMPLITUDE (dB)
 SOI ADC exhibits better frequency


1st
2nd
3rd
4th
5th
6th
7th
8th
9th
-20
-60
-80
-100
-120
-140
-160
0
ENOB vs SAMPLE RATE
4
6
8
10
ANALOG INPUT FREQUENCY (Hz)
12
BULK ADC
SOI ADC
6
FFT PLOT
0
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
-20
8
-40
AMPLITUDE (dB)
7
ENOB(bits)
14
x 10
(a) SOI CMOS ADC
10
9
2
6
5
-60
-80
-100
-120
4
-140
3
-160
2
20
22
24
26
28
30
32
SAMPLE RATE(Msps)
34
36
38
40
-180
0
2
4
6
8
10
ANALOG INPUT FREQUENCY (Hz)
(b) Bulk CMOS ADC
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14
6
x 10
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EXPERIMENTAL RESULTS
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TID Experiment
Experiment conditions
Radiation
•
•
•
•
•
Cobalt-60 gamma radiation source
at the room temperature
static bias state
dose rate of 50rad(Si)/s
irradiated to 500krad(Si)
Anneal
• static bias state
• 168 hours
• at 100℃
Measure point
pre-radiation, 50k, 100k, 150k, 300k, 500krad(Si) and
after anneal
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EXPERIMENTAL RESULTS
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SFDR vs TID
75
 TID Experiment
70
65
SFDR(dB)
 SOI ADC
 TID tolerance > 300krad(Si)
 Bulk ADC
 TID tolerance <50krad(Si)
60
55
50
45
BULK ADC
SOI ADC
CONSUMPTION vs TID
40
360
0
50
100
150
BULK ADC
SOI ADC
350
200
250
300
TID(krad(Si))
350
400
450
500
ENOB vs TID
10
330
9
320
8
310
ENOB(bits)
CONSUMPTION(mw)
340
300
290
7
6
280
5
270
260
BULK ADC
SOI ADC
0
50
100
150
200
250 300
TID(krad(Si))
350
400
450
500
4
0
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100
150
200
250
300
TID(krad(Si))
350
400
450
500
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EXPERIMENTAL RESULTS
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 SEE Experiment
 DC analog input signals
-0.8V, 0V and 0.8V
 At room temperature
LET_Cl
17MeV•cm2/mg
flux
104/cm2•s
fluence
107/cm2
Noise window
±4LSB
Expected
Digital Output
96-103，504511，920-927
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EXPERIMENTAL RESULTS
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 SEE Experiment
 SOI ADC
 SEL and SEFI

immunity
@LET = 63MeV·cm2/mg
SEU cross-section
•
3.1X10-6cm2/device @LET =
17MeV·cm2/mg
9.6X10-6cm2/device @LET =
63MeV·cm2/mg
•
Bulk ADC
 SEL and SEFI
•

-3
10
CROSS SECTION(cm2/device)
•
CROSS SECTION vs LET
-2
10
-4
10
-5
10
-6
10
BULK ADC
SOI ADC
-7
10
0
10
20
30
40
LET(MeV*cm2/mg)
50
60
70
immunity @LET = 63MeV·cm2/mg
single event upset (SEU) cross-section
•
two order of magnitude higher than SOI ADC
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CONCLUSION
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In conclusion, by implementing simple RHBD approaches
and taking the inherent advantage of the rad-hard SOI
technology, the SOI-based ADC achieves the TID tolerance of
300krad(Si) at least, nearly one order of magnitude higher
than bulk ADC, and the SEU cross-section of
6cm2/device
9.6X10-
at 63MeV·cm2/mg LET, lower than bulk ADC by
two orders of magnitude, more suitable for harsh radiation
environment applications.
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