Transcript Microsoft PowerPoint

ICs: The Driver for Information Technology
www.csl.uiuc.edu
Integrated Circuits: The Driver for
Information Technology
High-speed Information Transfer
CAD
IC Design
Project Goal: To demonstrate the benefits in power consumption
and BER offered through the use of Error Correction Coding in the
context of high-speed backplane I/O signaling (~5Gb/s).
Design
datapath
I/O Link Specs:
LDPC Decoder
MAP Decoder
EST
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Error-resilient
FIR Filter
ECC-based
On-chip Links
Estimator 1
devices
circuits
architectures
systems
• Circuits research at UIUC: devices to systems
• Overarching themes are
– power minimization
– adapting to and exploiting nanoscale technology
Memory Data
Estimator 2
Stochastic Sensor Network-on-a-Chip
DSP
RF FRONT END
IQ Modulator
IQ Demodulator
DAC
Digital Processing
Ref.
A/D
PA
ADC
ADF
m-1 MUX
A/Dm
...
...
fclk
...
Vin
PLL
Dout
Device technology scaling into nanometer region
has enabled CMOS design for RF Front End.
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“All CMOS” design gives low-cost chips for next
generation broadband wireless access: 4G
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Nano-scale CMOS designs pose an extreme
challenge: trade-off power efficiency, noise and
linearity.
• Today’s deep submicron technology is problematic for ASICs
– Cost of fabrication facilities and mask making has increased significantly
– Physical effects are increasingly critical for power, reliability and speed
– Design complexity is high
• An alternative: FPGA
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[S] and [Noise] Parameter Measurement for UWB LNA
Power Amplifier for Wimax
fclk/m
...
1-m DEMUX
VCO
SHA
900
LNA
DAC
ADF
DSP
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ADC
900
Proration
A/D1
FPGA: Field-programmable Gate Arrays
RF Circuits for Wireless Communication
The analog world meets digital processing at the ADC… It is the most prominent and widely used
mixed-signal circuit in today’s integrated mixed-signal circuit designs. The ADC is also a useful vehicle
for identifying advantages and limitations of future technologies with respect to system integration.
Proration
Estimator N
Estimator 3
Data Converters
Analog
Fusion
Block
– Synthesis with complicated clocking and timing constraints
– Synthesis for power reduction, e.g., glitch power and leakage power
– Process variation-aware synthesis
4Gs/s Track & Hold Amplifier
12
6
S21 (dB)
8
6
2
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4
Digitally equalized 1-GS/s 6-b low-power ADC for UWB radio
2
0
0
Prototype implemented in 130-nm digital CMOS with 1.2-V supply
CAD: An Enabling Technology for IC Design
• Modern complex ICs (nano-scale,
billions of transistors) cannot be
designed without computer-aided
design (CAD) software.
Specification
Architecture Design
• Sample CAD research at UIUC:
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Lithography-aware CAD
Chip-level wiring
Board-level wiring
Chip planning
Layout verification
CAD for low power design
Logic Design
Physical Design
Chip
NF50 (dB)
4
Chip layout (2×2 mm2)
SoC Integration
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Short total turnaround time
No or very low NRE (none-recurring engineering) cost
Field-reprogrammable for upgrade and bug fix
Suitable for low/medium volume production and prototyping applications
• CAD challenges for multi-million gate FPGAs
Low Noise Amplifier for UWB
10
fclk/m
5Gb/s data rate.
BER < 10-15 (post FEC).
10”, 20”, 34” channel lengths.
Power < 5mW/Gb/s.
0.18mm RF-CMOS process.
1st tape-out in 2007.
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4
6
8
10
• Design challenges for future FPGAs
– 3D integration
– CMOS/Nanomaterial hybrid FPGAs
– Fault tolerance
12
freq, GHz
IC Reliability and Manufacturability
• Charge exchange occurs
between materials with
dissimilar electron affinities
• Static discharges are
unavoidable during IC
manufacutring, system
assembly, product use.
• Typical current waveform at an
IC pin during an ESD event is
shown to the right.
• Such high currents cannot be
handled by nanoscale
transistors.
• On-chip ESD protection circuits
must be used.
• UIUC research on protection
circuit design, modeling and
test.
Poster Contributors
• Deming Chen
• Milton Feng
• Naresh Shanbhag
10 A
Current
1 ns
Time
Global Infotech: Pathways to the Future with Global Partnerships
• Yun Chiu
• Elyse Rosenbaum
• Martin Wong
– Faculty members in Electrical and Computer
Engineering
– Research programs conducted in the
Coordinated Science Laboratory
– Research sponsors: NSF, SRC, DARPA, and
industry