Transcript Analog to Digital Converters

Analog to Digital
Converters
• Slow (Ramp)
• Medium (Successive Approx)
• Fast (Flash)
• Oversampling (S-D)
Key components:
Comparitors
Sample-and-Hold
D/A converters
Sample
And Hold
+
Comparitors(s)
D/A(s)
Digital Outputs
Analog Input
Basic A/D Structure
Digital Control
Comparitors
• quantizing unit of ADCs
Nonideal aspects:
• Input offset voltage (static characteristic)
• Propagation time delay
- Bandwidth (linear)
- Slew rate (nonlinear)
Slow-Speed A/D Converters
Successive Approximation
Successive Approximation
Successive Approximation Algorithm:
1.) Start with the MSB bit and work toward the LSB bit.
2.) Guess the MSB bit as 1.
3.) Apply the digital word 10000.... to a DAC.
4.) Compare the DAC output with the sampled analog input voltage.
5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, change the guess to 0.
6.) Repeat for the next MSB.
If the number of bits is N, the time for conversion will be NT where T is the clock period.
Successive Approximation
5bit Successive Approximation ADC
More Details on the DAC
Pipeline Algorithmic ADC
Each stage: x by 2,
+ or – by Vref
Self-Calibrating ADC
Parallel / Flash A/D Converter
Number of comparator required is 2N-1
Typical sampling frequencies
can be as high as 400MHz
for 6-bits in sub-micron
CMOS technology.
Interpolating ADCs
Must get the gain within ½ LSB accurate.
Folding ADCs
Schematic of a 5bit Folding ADC
Folding Circuits
Folding and interpolation ADCs offer the most resolution at high speeds (≈8 bits at 200MHz)
Need discussion for floating-gate Flash ADCs
If no offset at all, then sizing of devices can be optimized for
speed.
Therefore small input transistors: highest speed, and lowest
input capacitance….if smallest cap in a typical 0.35um process,
gate input capacitance is approximately 1fF; therefore a 6bit
would have an input capacitance of ~100fF with parasitics accounted for,
which is small enough…. (would need ~1kOhm output resistance for a S/H to settle in 1ns
Do we need S/H block here?
Need pictures here.
Two-Step Flash ADC
Simple 4-bit Flash Converter
Pipelined Flash ADC
Part of a Two-Step ADC
PIPELINE ADC WITH DIGITAL
ERROR CORRECTION
Vin
S/H
2N1
+
S/H
-
ADC-N1 bit
2N2
+
S/H
-
-
DAC-N1 bit
ADC-N2 bit
DAC-N2 bit
2N3
+
ADC-N3 bit
DAC-N3 bit
VREF
3 bits
N3 bit REG
3 bits
N2 bit REG
N2 bit REG
3 bits
N1 bit REG
N1 bit REG
4 bits
S/H
N1 bit REG
0.5 LSB offset
0.5 LSB offset
The ADC of the first stage uses 16 equal capacitors instead of 4 binary weighted for more accuracy
12-BIT PIPELINE ADC