Transcript ppt - Belle II

Sensor and ASIC R&D
Hans-Günther
Moser
MPI für Physik
Sensor Prototype Production: running,
ASICs:
Switcher, DCD
Prototypes under test,
DHP: design phase
More Information: Indico page of Ringberg
Workshop:
http://indico.mppmu.mpg.de/indico/conferenceTimeTable.
py?confId=466
SuperKEKB
3nd open meeting
July 7-9, 2009
Sensor Production Status
Status at 2nd Belle II meeting (March): SOI wafer bonding at Tracit, France
Hans-Günther
Moser
MPI für Physik
SuperKEKB
3nd open meeting
July 7-9, 2009
30 SOI wafers received, processing in our own lab has started
Presently: cleaning, oxygenation, alignment mask, first implantation: next
week. Processed are 6 wafers + dummies
Wafer layout
Hans-Günther
Moser
MPI für Physik
Small test matrices
with various pixel
sizes;
50 µm x 50 µm
..
50 µm x 175 µm
Technology
variations
(gate length L)
4 ½ module large
matrices with most
likely pixel sizes
5cm: 50µm x 75µm
5cm: 50µm x 100µm
3.5cm 50µm x 50µm
3.5cm 50µm x 75µm
SuperKEKB
3nd open meeting
July 7-9, 2009
Important for timing!
Favorized design (zoom)
Hans-Günther
Moser
MPI für Physik
SuperKEKB
3nd open meeting
July 7-9, 2009
Favorized design (zoom)
Hans-Günther
Moser
MPI für Physik
Gate
Pixel
Clear
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Drain
Source
Option: common source/drain: very
compact (small pitch) but interleaved
readout
1
2
3
To gate switcher
5
4
6
7
8
To DCD
Hans-Günther
Moser
MPI für Physik
3
2
4
5
76
8
1
3
2
4
5
76
8
1
3
2
4
5
76
8
1
3
2
4
5
76
8
1
Source (all connected, double pixel share one source)
Drain (neighbour pixel share one drain, connected to one DCD channel)
SuperKEKB
3nd open meeting
July 7-9, 2009
Gate (double pixel have gates connected & interleaved connection)
DEPFET parameter model
Read-Clear-Read for 3 neighboring matrix rows
Including realistic RC loads for control and readout lines
Hans-Günther
Moser
MPI für Physik
1. row
2. row
3. row
clear
clear
clear
gate
drain current
“1“
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“0“
gate
“0“
“0“
gate
“1“
“0“
RC times critical: 80 ns sample-clear-sample just ok
Capacitance depends on sensor length (drain lines) and number of pixels (drain
capacitance)
Changes for final production
Hans-Günther
Moser
MPI für Physik
Thin oxides: for improved radiation hardness: dox 200nm -> 100nm
=> small threshold voltage shifts
=> however: reduction of gain

dI d  
q s
Id µ


gq 
 2 VG 
 Vth    2 3
dq s L 
C oxWL
L WC ox

Shorter gates
compensate gain loss due to thin oxide
-> compensate by reducing L by 0.8 (6 µm -> 4.7 µm)
improve gain (overcompensate)
L ~ 4.0µm: gq ~ 600 pA/e (instead of 450 pA/e)
needs plasma etching
SuperKEKB
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July 7-9, 2009
Tests/test structures on PXD6 production
Extra thin oxide test planned in autumn
DEPFET Readout and Control ASICs
15mm
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Moser
MPI für Physik
50µm
~75µm
clear[n+1]
gate[n+1]
98 mm
132 mm
clear[n]
gate[n]
drain lines
Switcher chips (line driver)
cross section
(height not to scale)
thinned active pixel area
DCD chips (analog)
DHP chips (digital)
SuperKEKB
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DCD, Switcher: Heidelberg
DHP: Bonn, Barcelona
flex cable
Switcher 3
9V
Switcher 3
Radiation tolerant layout
in 0.35 μm technology
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Moser
MPI für Physik
‘SRAM’
128 channels
+ Very fast
6V
- Operation up to 11.5 V
Novel design: Uses stacked
LV transistors, HV twin-wells
and capacitors as levelshifters
‘SRAM’
+ No DC power consumption
‘SRAM’
3V
6V
out
Tested up to 22 Mrad
3V
2ns
‘SRAM’
9V
0V
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July 7-9, 2009
Switcher 4
Switcher 4
Uses radiation tolerant high
voltage transistors in HV 0.35 μm
technology
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Moser
MPI für Physik
64 channels
+ fast enough
+ Possible operation up to 50 V (30V
tested)
+ low DC power consumption
Enclosed design of NMOS HV
transistors
Should be rad hard (to be tested)
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Final chip: only 16 or 32 channels
DCD
» - Technology 0.18 μm
» - 72 Channels
» - 2 ADCs and regulated cascode/channel
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Moser
MPI für Physik
» - 6 channels multiplexed to one digital LVDS output
» - ADC sampling period 160 ns (8 bits)
» - Channel sampling period 80 ns
» - LVDS output: 600 M bits/s
» - Chip: 7.2 G bits/s (12 outputs)
» - Radiation tolerant design
» - ~ 1mW/ADC
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DCD
Radiation hardness tested up to 7 Mrad
Hans-Günther
Moser
MPI für Physik
Layout for Belle II: 160 channel chip, bump bonded
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DCD Tests
Hans-Günther
Moser
MPI für Physik
Manuel Koch, Bonn
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Works almost at design frequency (540 MHz: 88ns line rate)
(works still at nominal 600 MHz, but with higher noise)
Noise level: 90nA with 450 pA/e: 200 e ENC (S/N = 20:1)
Some bugs discovered, improved version will be submitted
Push DEPFET gain (600 pA/e ?)
DHP
Hans-Günther
Moser
MPI für Physik
Configuration
Synchronization DCD/Switcher
Data processing (CM, Pedestal 0-Sup)
Clustering?
Buffering,
Trigger handling
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Being designed, 90nm CMOS
DHP – Signal Rates & Data Flow
960 r/o lines from DEPFET matrix
160
to Switcher & DCD
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Moser
MPI für Physik
JTAG
timing
160
ADC
160
ADC
160
ADC
160
ADC
ADC
160
ADC
DCD DCD DCD DCD DCD DCD
40
40
40
40
40
40
12.8 MHz line freq.
(sample rate)
DCD chips:
- 8 bit ADC per input channel
- 4 channels per output
98 Gbit/sec
(410 MHz output data x 240 lines)
de-serializer
PLL
common mode & pedestal
correction
raw data
memory
zero suppression
conf.
pedestal
memory
de-randomizing buffer
DHP chips (one per DCD):
- raw data correction
- zero supression à 18 Gbit/sec
- trigger r/oà 1.8 Gbit/sec
JTAG
SER
Gbit link
JTAG
clock, sync
data out
DHP
DHP
DHP
trigger
1.8 Gbit/sec
Assumptions (à extended specs.)
Bonn, Barcelona
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»
10µs r/o time (à 20 µs)
»
128 switcher channels (à 256)
»
10 kHz trigger (un-triggered r/o)
»
2-4% occupancy
Summary: ASICs
»- DCD prototype chip has been tested with test signals that correspond to DEPFET
currents and irradiated up to 7 Mrad.
» The chip works fine and has high enough conversion speed.
Hans-Günther
Moser
MPI für Physik
» Operation with matrices still to be tested – we do not expect problems.
» Only „fine tuning“ of the design for the super KEKB operation is necessary.
»- Switcher prototype with LV transistors has been tested and irradiated up to 22 MRad.
» The chip works fine and has adequate speed for Belle II operation.
»- Another prototype with HV transistors has been designed and tested.
»- The irradiation of the chip still has to be done but the basic and most critical part (highvoltage NMOS) has been irradiated up to 600 KRad and no damage has been observed.
»- DHP chip will be designed using digital design tools in intrinsically radiation hard 90 nm
technology.
»- Choice between 4 different bumping technologies – advantages and disadvantages still to
be evaluated
»Planned submissions:
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•
Switcher:
October 09
•
DCD:
September 09
•
DHP:
October 09
Questions
Hans-Günther
Moser
MPI für Physik
General:
Radiation: SEU tolerance: what level of background from hadrons?
Ground loops?
DHP
Trigger: max. rate and trigger dead time
Interleaved readout: not wanted by ASIC designers
Distance DHP-DHH
How many (complete) frames to store (for calibration)
Switcher:
Range of different operation voltages (compatible with internal level shifter)
SuperKEKB
3nd open meeting
July 7-9, 2009