Transcript A radiation-tolerant LDO voltage regulator for HEP applications

Power distribution in SLHC
trackers using embedded DC-DC
converters
F.Faccio, G.Blanchot, S.Michelis,
C.Fuentes, B.Allongue, S.Orlandi
CERN – PH-ESE
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Outline

Proposed scheme using DC-DC converters
 Specific technical difficulties
 Semiconductor technology
 EMC (conducted and radiated noise)
 Inductor design
 ASIC development and integration aspects
 Conclusion
PH seminar, Jan09
F.Faccio, PH/ESE
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SLHC-specific requirements

Converters to be placed inside the tracker
volume
Magnetic field (up to 4T)
Radiation field (>100Mrd, >1015n/cm2)
Environment sensitive to noise
(EMI)

No commercial component exists,
need for a custom development
PH seminar, Jan09
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Proposed distribution scheme
(ATLAS Short Strip concept)
Voltage for SMC and optoelectronics generated locally by a converter stage 1
Rod/stave
10-12V
Distribution with 2 conversion stages





It is composed of 2 converters
It generates 2 intermediate power buses (2.5 for
analog and 1.8 for digital)
It provides 1.6W for analog and 2W for digital, but
could provide more than 2x that power – allowing
to power 4 hybrids with even higher efficiency if
mechanical integration allows it
Stage 2:



2 Converter stage2 on-chip
Only 1 line to the stave (10-12V), all other voltages
generated locally
Stage 1:
Detector

Switched capacitor converter with fixed conversion
ratio = 2
It is integrated directly on-chip (2 per chip, analog
and digital)
Efficient because able to provide locally the voltage
required by the load (different for analog and digital)
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Hybrid
controller
10-12V
2.5V bus
1.8V bus
2 Converter stage 1
4
Offered modularity
Easy control



Module power turned on/off
by SMC via serial bus to DCDC converters in stage 1
FE ASIC individually turned
on/off by HC via serial bus
Other configurations
possible, for instance:


Individual converter composition



HC powered via separate
2.5V line under the
control of SMC
DC-DC converters on
module controlled by HC)
DC-DC ASIC in plastic package (~7x7x1 mm)
A few SMD components
Air-core inductor

Size dependent on chosen design (to be
discussed later)
2.5V power bus
1.8V power bus
Serial “chip enable”
bus from HC
DC-DC
HC
10-12V
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Serial “module enable”
bus from SMC
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Outline

Proposed scheme using DC-DC converters
 Specific technical difficulties
 Semiconductor technology
 EMC (conducted and radiated noise)
 Inductor design
 ASIC development and integration aspects
 Conclusion
PH seminar, Jan09
F.Faccio, PH/ESE
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Semiconductor technology

The converter requires the use of a technology able to work up to at
least 15-20V


High-voltage technologies are typically tailored for automotive
applications




Such technology is very different from the advanced low-voltage (1-2.5V) CMOS
processes used for readout and control electronics, for which we know well the
radiation performance and how to improve it
Need to survey the market and develop radiation-tolerant design techniques enabling
the converter to survive the SLHC radiation environment (> 10Mrd)
A 0.35mm technology has been extensively tested (see next slide)
In the near future, 3 other technologies will be tested in the 0.18-0.13mm nodes
Properties of high-voltage transistors largely determine converter’s
performance

Need for small Ron, and small gate capacitance (especially Cgd) for given Ron!
Prototypes in 0.35mm
PH seminar, Jan09
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Candidate technologies
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All technologies offer “low voltage” devices from a mixed-signal technology, with
the addition of a “high-voltage” module (up to 80V in some cases)
Some properties of the high-voltage transistors are summarized in the table
below (for NMOS transistors, that have to be used as switches)
Tech
Node
(um)
Trans
type
Max
Vds
(V)
Vgs
(V)
Tox
(nm)
Ron*um
(kOhm*um)
Status
0.35
Lateral
Vertical
14
80
3.5
3.5
7
7
8
33
Tested
0.18
Lateral
20
5.5
12
4.75
Tested
0.13
Lateral
20
4.8
8.5
7
Tested
0.25
Lateral
20
2.5
5
4-5
Tested
0.18
Lateral
20
1.8
4.5
9.3
First MPW April 09
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Examples of TID effects (NMOS)
Leakage (large increase)
Id=f(Vg) for Vds=14V
Id=f(vg) in logarithmic scale
1.0E-2
1.00E-01
1.0E-3
1.00E-02
1.0E-4
1.00E-03
1.0E-5
1.00E-04
Ids (A)
Id (A)
1.00E-05
1.00E-06
1.00E-07
1.00E-08
prerad
1.00E-09
300krad
1.00E-12
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
5 Mrd
63 Mrd
93 Mrd
1.0E-9
350 Mrd
annealing
1.0E-10
21Mrad
1.00E-11
1 Mrd
1.0E-7
1.0E-8
1Mrad
1.00E-10
prerad
1.0E-6
3.0
3.5
1.0E-11
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
Vgs (V)
Vg (V)
Id=f(Vg) for Vds=12V
1.0E-1
Large Vth shift
1.0E-2
No leakage, small Vth shift
1.0E-3
Ids (A)
1.0E-4
1.0E-5
prerad
1.0E-6
1Mrd
1.0E-7
10Mrd
80Mrd
1.0E-8
100Mrd
1.0E-9
166Mrd
258Mrd
1.0E-10
1.0E-11
-0.5
annealing
0.5
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1.5
2.5
Vgs (V)
3.5
4.5
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Examples of displacement damage
effects
Effect visible in output characteristics [Id=f(Vds)]
Id=f(Vg) for Vgs=2.5V
Id=f(Vg) for Vgs=4.5V
3.0E-3
prerad
3.5E-3
5e14 p/cm2
1e15 p/cm2
3.0E-3
2.5E-3
2e15 p/cm2
5e15 p/cm2
2.0E-3
1e16 p/cm2
2.0E-3
Ids (A)
Ids (A)
2.5E-3
1.5E-3
1.5E-3
prerad
5e14 p/cm2
1.0E-3
1.0E-3
1e15 p/cm2
2e15 p/cm2
5.0E-4
5.0E-4
0.0E+0
0.0E+0
5e15 p/cm2
7e15 p/cm2
1e16 p/cm2
0.0
2.0
4.0
Vds (V)
6.0
8.0
10.0
0.0
2.0
4.0
6.0
8.0
Vds (V)
10.0
12.0
14.0
… and in on-resistance (Ron)
NMOS, Ron (Vgs=2.5V)
NMOS, Ron (Vgs=4.5V)
400%
LDN_10_06
200%
LDN_10_5
250
Equivalent TID
200
300%
150
200%
100
350
LDN_07_90
300
Ron variation (%)
500%
LDN_10_05U
Equivalent TID (Mrd)
Ron variation (%)
600%
250%
350
300
LDN_06
Equivalent TID
150%
250
200
150
100%
100
50%
100%
0%
1E+13
50
50
1E+14
1E+15
Proton fluence (p/cm 2)
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1E+16
0%
1E+13
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1E+14
1E+15
Proton fluence (p/cm 2)
0
1E+16
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Equivalent TID (Mrd)
700%
Summary of results

One technology (0.25mm node) has demonstrated radiation tolerance
compatible with benchmark:

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NMOS Ron decrease below 60% for 2.5∙1015 n/cm2 (1MeV equivalent)
Vth shift manageable (below 200mV for NMOS, 400mV for PMOS @
350Mrd)
Negligible leakage current with TID
Overall, radiation could affect converter performance as small drop of
efficiency (below 5%)

One technology (0.13mm node) could satisfy requirements for
installation further from collision point, where fluence is limited below
1∙1015 n/cm2 (1MeV equivalent)
 The other 2 technologies are less performant and will not be considered
further
 Conclusion:

While starting prototype work in the 0.25um technology, another 0.18mm
technology will be tested in 2009 (we look for a second source with
comparable radiation performance)
PH seminar, Jan09
F.Faccio, PH/ESE
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EMC issues


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Without any doubt, switching converters inside the tracker are an additional source of noise
Noise can be conducted (via the cables) or radiated (near-field emission from inductor, loops,
and switching nodes). Both propagation paths have to be controlled
Action is required in 2 directions


Decrease the noise from the source
Control the noise path – ultimately design a more robust system
EMI (dV/dt)
EMI (dψ/dt)
EMI (dI/dt)
EMI (dI/dt)
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Conducted CM noise from custom
prototypes

Several custom DC-DC prototypes (buck topology) using discrete
commercial components have been manufactured
 Proper design of PCB and choice of passive components (caps)
drastically decrease the conducted noise
Noise (dBuA)
“Reference” level based on Class A limit from
CISPR11 converted to current on a given
impedance (Careful: this is NOT a real limit)
Frequency (Hz)
Frequency (Hz)
Example: output common mode noise for 2 custom prototypes using identical discrete components
(commercial driver + switches). Only the design of the PCB and the passive components differ
PH seminar, Jan09
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Radiated noise (magnetic field)
The susceptibility of systems to the magnetic field emitted by inductors of power converters is a
major concern. System tests were carried out on TOTEM, with a coil driven by an amplified RF
source. The coil is accurately positioned above the detector, the bondings and the ASICs and the
induced noise is analyzed from the test DAQ.
538 nH air core, 1A.
Noise decreases when the inductance is placed
at some distance from the detector
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Straight on bondings
Noise
[ADC Counts]
12
10
8
6
4
2
0
0
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20
Distance
[mm]
25
30
35
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Susceptibility to Magnetic Field
Shielding of inductor (Al wrap)
The shielding of the coil with Al foil allows protecting the front-end against radiated noise
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Powering a Si Strip module with
DC-DC converter prototypes
The front-end ASICs were powered by a DC/DC converter prototype (PH-ESE) – switching
frequency = 1MHz
•Measurements on the TOTEM Si Strip module, with
detector biased
•3 locations were exercised, with no impact on the
noise performance of the system
•Cables were still relatively long in this test
•When powered with very short cables, marginal
noise increase for only 1 prototype (no noise increase
for another)
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• DCDC mounted on top of the detector
without shield, d < 15 mm to be able to
see some coupling effect
• This is radiated noise (cables as in
previous measurements, hence no
influence of conducted noise as before)
•Main radiated field from inductor. We
need to shield the inductor
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Requirements for the inductor
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Value: up to 500-700nH (this is feasible with
air-core)
Compact for high integration
Light for low material budget
With small ESR both in DC and AC (at the
switching frequency) for high efficiency
It needs to be shielded for low radiated noise
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Different air-core inductors

Air-core inductors can be manufactured in different configurations:
planar, solenoid, toroid
Planar (on PCB)
ESR(DC)>100mW
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Solenoid
ESR(DC)~10-30mW
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Toroid
ESR(DC)~20-30mW for custom
winding, largely dependent on
implementation for PCB toroid
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“Optimized” PCB toroid (1)
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
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Custom design exploiting PCB technology: easy
to manufacture, characteristics well reproducible
Design can be optimized for low volume, low
ESR, minimum radiated noise
With the help of simulation tools (Ansoft Maxwell
3D and Q3D Extractor), we estimated
inductance, capacitance and ESR for different
designs. This guided the choice of the samples
to manufacture as prototypes
The addition of two Al layers (top, bottom)
shields the parasitic radiated field efficiently
-2
10
150nH solenoid unshielded
Standard 150nH PCB toroid
150nH PCB toroid shielded
-3
Magnetic induction [T]
10
-4
10

-5
10
-6
10

-7
10
0
2
4
6
8
10
Distance from the border of the inductors [mm]
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A series of PCB toroids has
been designed and is now
being manufactured
Measurements will be
compared to simulation
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Outline

Proposed scheme using DC-DC converters
 Specific technical difficulties
 Semiconductor technology
 EMC (conducted and radiated noise)
 Inductor design
 ASIC development and integration aspects
 Conclusion
PH seminar, Jan09
F.Faccio, PH/ESE
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ASIC development – 1st generation

ASIC designer: Stefano Michelis
 Prototype for “conversion stage 1”
 First prototype designed and
manufactured in AMIS I3T80
technology
 Simple buck topology




Vin up to 10V
Vout=2.5V
Iout up to 1.5A
switching frequency 0.3-1.2 MHz
12
10

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6
Voltage (V)
ASIC included main functions only
(switches, control circuitry)
 External compensation network,
reference voltage and sawtooth
generator required
 Functionality tested OK
 Prototype used already to power
detector modules
4
2
0
-2
Vin
Vind
Vout
-4
-6
-1
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-0.5
0
time (s)
0.5
1
-6
x 10
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ASIC development – 2nd generation

Second generation prototype
 Still manufactured in AMIS 0.35mm
 Features:










VIN and Power Rail Operation from +3.3V to +12V
Selectable output voltage (nominal 2.5V)
Maximum output current: 3A
Fast Transient Response - 0 to 100% Duty Cycle
14MHz Bandwidth Error Amplifier with 10V/μs
Slew Rate
Internal oscillator fixed at 1Mhz, programmable
from 400kHz to 3MHz with external resistor
Internal voltage reference (nominally (1.2V)
Remote Voltage Sensing with Unity Gain
Programmable delay between gate signals
Integrated feedback loop with bandwidth of 20Khz

Submitted December 08, expected back
in April 09
 Mounted in 7x7mm QFN package
PH seminar, Jan09
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Towards integration



Compact design

Reducing the size of the full
converter

Design compatible with tracker
layout (evolving) in terms of
area, volume, material budget,
cooling
System tests

Use converter prototypes to
power available system
prototypes (evolving)
Develop prototypes of conversion
stage 2 (on-chip switched capacitor)
to demonstrate efficiency and
compatibility with FE circuitry
PH seminar, Jan09
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Inductor
ASIC SMD devices
PCB substrate
2 converters (analog
and digital power)
Integration in ATLAS SCT module design
From D.Ferrere
University of Geneva
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Outline

Proposed scheme using DC-DC converters
 Specific technical difficulties
 Semiconductor technology
 EMC (conducted and radiated noise)
 Inductor design
 ASIC development and integration aspects
 Conclusion
PH seminar, Jan09
F.Faccio, PH/ESE
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Conclusion




Distributing power is SLHC trackers requires a
different scheme than what has been used for LHC
trackers
The use of DC-DC converters enables to meet the
requirements, but implies the availability of “custom”
converters (radiation, magnetic field, EMC)
Technical difficulties for the successful development
of the converters are being solved. Converter design
for integration in final system is evolving
PH R&D program and EU FP7 SLHC-PP program
provide essential resources for this crucial
development
PH seminar, Jan09
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