Transcript presentation

R/2R DAC w/ SPI interface for
the IBM 130nm Process
Larry Ruckman
Physics 476
28April2010
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Motivation
• Want to have a digitally controlled voltage
reference that’s exactly referenced to the
ASIC VDD
• Increase electronic packing density by
stuffing the DAC into the ASIC
• Decrease production cost by not having to
buy DAC ICs from a semiconductor
company
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Overall Block Diagram
SPI STRB GEN
12x REGs
R/2R
Ladder
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R/2R Ladder
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DAC_BIT
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12 Bit Simulation
• LSB = (1.2 V)/(2^12) = 293 mV/count
• Theoretical slope agrees with simulation
• Slope errors in measurement will come from fabrication
tolerances/errors
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SPI Timing and REGs
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Serial Protocol Interface (SPI)
AD5324 DAC SPI example Timing Diagram
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My DAC’s SPI Timing Diagram
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STRB Timing Simulation Check
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DAC w/ SPI REGs Layout
• 129.07 um by 51.23 um
• Uses 1176 transistors in this design
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Status/Summary
• Top Level of my design (test structure) has
passed both design checks
– LVS = Assura
– DRC = Calibre
• Pin Count: 3 Analog, 3 Digital Inputs = Total 6
• Space Requirement: 129.07 um by 51.23 um
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