Transcript System Architecture for Reconfigurable Platform

Module2: System
Architecture for
Reconfigurable Platform
최해욱 (ICU, 공학부)
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
목 차
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Module 1 : SoC System Specification, Language, Model, Analysis
Module 2 : System Architecture for Reconfigurable Platform
- Platform-based Design and Platform Architecture
- IP-based Design, Virtual-component-based Design
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) 목차
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System-on-Chip Architectures
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SoC Design Methodology
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Platform-based Design
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Configurable Processor Cores
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) System-on-Chip Architectures
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A system-on-chip architecture integrates several
heterogeneous components on a single chip
Memory
Microcontroller
AnalogDigital
Communication
Structure
DSP
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FPGA
DigitalAnalog
Custom
Hardware
Increasingly powerful applications are possible!
An efficient implementation requires many low
level details
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) A typical system-on-chip
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A typical system-on-chip on a single chip
Memory
Micro-processor
Custom
Logic
(ASIC)
DSP
I/O
System on a chip
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
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Canonical form of an SoC
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A microprocessor and its
memory subsystem
On-Chip buses
A memory controller for external
memory
A communications controller
A video decoder
A timer and interrupt controller
A general purpose I/O (GPIO)
interface
A UART interface
Memory
MicroProcessor
I/O
Control
BUS
BRIDGE
Video
Decoder
Memory
Ctrl
TIMER
GPIO
INTR
CTRL
UART
DRAM
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) SoC Architectures
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A SoC integrates many heterogeneous
components on a single chip
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A SoC is a parallel architecture and thus the
work on parallel computers can be used
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A key challenge is to design the
communication between the different entities
of a SoC in order to minimize the
communication overhead
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) How to design future embedded systems?
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Specification
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Idea
abstract
(Specification)
Design
o Design productivity increases with the level of
abstraction
o The task of functional verification is very difficult
at low abstraction levels
Abstraction
Gap
Implementation
o Efficient implementations require to exploit the
low-level features of the target architecture
detailed
Product
(Implementation)
Challenge for
System Design!
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Abstraction Levels
SYSTEM
CHIP
REGISTER
GATE
CIRCUIT
SILICON
It is important to work on the right level of abstraction!
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) System Level
IMU
A/B
Computer
Radar
C/D
IMU: Interrupt Managing Unit (?)
C/D: Carrier Detection (?)
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Chip Level
RAM
16
uP
Pararllel
Port
8
USART
Interrupt
Controller
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Register Level
Sel
Reg
MUX
Clk A
Reg
Clk B
Inc
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Gate Level
Cout
A
P
Sum
B
Cin
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Transistor Level
Vdd
GP
SP
DP
Vout
Vin
DN
GN
SN
GND
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Layout (Silicon) Level
Vin
GND
Vdd
Vout
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) The importance of the level of abstraction
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The right level of abstraction allows to make the
appropriate decisions without considering
unnecessary details
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Shorter design times
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Though in theory everything can be fine-tuned at
the silicon level, it is in practice impossible to
make a large design at the silicon level
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) SoC Design
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The continuous progress in silicon process
technology allows to increase more and more
functionality on a single chip => Systems on a
chip become reality
Market-driven forces:
o Shorter product design schedules and life spans
o Products have to confirm to standards
o The design has to be right from the start. An
implementation error means heavy loss of money or
product death
o Large designs are integrated into a single chip
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The SoC design process must address these
driving forces
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Primary Design Methodologies
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Area Driven Design (ADD)
o Digital ASIC on older process technologies
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Timing-Driven Design (TDD)
o Digital ASIC on Deep Submicron (DSM)
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Block-Based Design (BBD)
o Complex ASIC with Intellectual Property Blocks
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Platform-Based Design (PBD)
o System-on-a-chip
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Area-Driven Design (ADD)
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Earlier process technologies were not able to
integrate very many transistors on a single chip
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Area was very important and the effort was put on
logic optimization
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ADD was used mainly for new designs (no reuse)
Logic
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Timing-Driven Design (TDD)
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With continuous improvements in process
technologies, area became less important
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Focus shifted to performance (speed and power)
constraints
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Time-to-market became increasingly important
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TDD is used for new designs on DSM processes
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Design teams are small
Logic
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Timing-Driven Design (TDD)
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TDD became possible due to:
o Interactive floor-planning tools, which gave good area and
delay estimates
o Static-timing analysis tools, which inform the designer, if
timing requirements are violated
o Compiler (synthesis) tools, which move the design to
higher levels of abstraction
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)
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Improved process technologies allow to put
additional components on a single chip (memory,
microprocessor cores)
Applications are more complex and are very difficult
to design and verify, if developed from scratch
Multiple design teams work on different parts of the
system
Reusable virtual components (VCs) can be acquired
from other companies
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DSP Core
Memory
IP-Block
Logic
Complex ASIC
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)
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Ideally a BBD is behaviorally modeled at the system
level
HW/SW trade-offs, functional HW/SW co-verification
is ideally performed at that level
Design is partitioned into several components, which
are then designed at a lower level (RTL for HW)
Then the entire design is verified (integration test)
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)
System
Model
Partitioning
& Mapping
HW-Model
(VHDL)
SW-Model
(C/C++)
HW
Synthesis
SW
Compilation
Netlist
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Verification
Executable
Program
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)
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BBD has been possible due to:
o High-level system analysis tools
o Block floor planning
• Constraint budgets for top-level chip interconnects
• Infrastructure models for clock, test, and bus architectures
that can be used for timing abstraction
o Integrated synthesis and physical design
• The influence of physical design issues is handled in the
synthesis process (better tools)
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Platform-Based Design (PBD)
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Deep Submicron Technologies allow to put many
components on a single chip
The costs for test and verification are continuously
increasing
Design Reuse is a prerequisite to enable PBD and
shortens Time-To-Market
ATM
RAM
MPEG
ROM
DSP Core
Proc Core
System-on-a-Chip
Logic
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Platform-Based Design (PBD)
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Like BBD, PBD starts at System Level (similar design flow)
PBD is heavily based on design reuse
Pre-verified blocks with standardized interfaces are used
The following design concepts must be further developed:
o Interface Standardization
o Virtual Component Design
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Objective: Plug & Play Design
Important: Standardized Test Strategies that can be used
for systems consisting of several components
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Platform-Based Design (PBD)
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PBD becomes possible due to
o System-level and architectural design tools and methodologies
o Physical Layout Tools
• Bus planning
• Block Integration
o Virtual Components functional verification tools
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There is a key problem with Virtual Components
(IP-blocks): IP-vendors do not want to reveal the internal
secrets of their designs!
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Configurable Processor Cores
Why Configurable Processor Cores?
 Observations
o Time-to-market is critical
o Development time for software is much smaller than for hardware
o Hardware can be customized and has much better performance than
software solution
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Configurable Processor Cores
Why Configurable Processor Cores?
 Idea
o Combine the advantages of hardware and software in form of
a customizable processor to achieve
• Clearly shorter Time-To-Market than hardware
• Clearly better performance than software
o Provide a processor platform with a basic architecture that can be
extended
• by additional optimized units (MAC, Floating-Point Unit)
• Own instructions together with own customized hardware can be
defined for the processor
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Example for a configurable processor: Xtensa(Tensilica)
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The Xtensa processor core
o Targets system-on-chip applications
o Is configurable, extensible and synthesizable
o Has
• Base Instruction Set Architecture
• Configurable Functions (Parameterized)
• Optional Functions
• Designer-Defined Functions and Registers
(For Acceleration of Specific Algorithms)
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Basic Xtensa Core
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32-bit architecture
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Base configuration:
o 32-bit ALU
o Up to 64 general purpose registers
o 6 special purpose registers
o 80 base instructions
o Improved 16- and 24-bit RISC instruction encoding
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Optional Architecture
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Execution Units
o Multipliers, 16 and 32 bits
o MAC-Unit, Floating-Point Unit
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Interface Options
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Memory Subsystem Options
o Memory Management Options
o Local Data and Instruction Caches
o Separate RAM, ROM Areas for Data and Instruction
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Tensilica Extension Language
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The Tensilica extension language is used to describe
new instructions, registers and execution units that
are then automatically added to the Xtensa processor
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Xtensa Processor Design Process
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The Tensilica extension language is used to describe
new instructions, registers and execution units that
are then automatically added to the Xtensa processor
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Design Flow
1. Choose basic Xtensa processor
2. Specify algorithm in C
3. Compile to Target Processor
4. Profile and check, if design constraints are met
5. If constraints are met, everything is fine, otherwise
6. Choose optional functions (e.g. Multiplier) or design
new instructions for the critical part => improved
architecture
7. Adjust your code for the new architecture
8. Go back to 3.
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Summary (Configurable Processor)
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The Xtensa concept provides
o Not only a configurable architecture
o But also a design methodology
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The idea is to take the best of both the hardware and
the software world in order to
o Have good performance
o Short Time-to-Market
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Xtensa processors can be used as parts of a systemon-chip architecture
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Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈) 참고문헌
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“System Modeling – Model of Computation and their Applications,” Axel
Jantsch LECS, Royal Institute of Technology, Stockholm, Sweden Jan,
2004.
“Winning the SoC Revolution-Experiences in Real Design,” Grant Martin
& Henry Chang, Cadence Labs, KAP, Jun, 2003.
“System Design and Methodology: Modeling and Design of Embedded
Systems,” Petru Eles, Linkopings Univ., Sweden
“Memory Issues in Embedded Systems-on-Chip,” Preeti Ranjan Panda
(Synopsys, Inc.), Nikil Dutt (Univ. of Cal/Irvine), Alexandru Nicolau
(Univ. of Cal/Irvine), KAP 1999.
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