Transcript Low Power System Level Design Methodologies

L32:Low Power System
On Chip
Jun-Dong Cho
SungKyunKwan Univ.
Dept. of ECE, Vada Lab.
http://vada.skku.ac.kr
1
Introduction to SOC
• SOC will bridge the gap b/w s/w and their implementation
in novel, energy-efficient silicon architecture.
•In SOC design, chips are assembled at IP block level
(design reusable) and IP interfaces rather than gate level
•SOC specs are coming from ICT system engineers rather
than RTL descriptions.
Common Fabric for IP Blocks
• Soft IP blocks are portable, but not as
predictable as hard IP.
• Hard IP blocks are very predictable since a
specific physical implementation can be
characterized, but are hard to port since are
often tied to a specific process.
• Common fabric is required for both
portability and predictability.
• Wide availability: Cell Based Array, metal
Four main applications
• Set-top box: Mobile multimedia system,
base station for the home local-area network.
• Digital PCTV: concurrent use of TV,3D
graphics, and Internet services
• Set-top box LAN service: Wireless homenetworks, multi-user wireless LAN
• Navigation system: steer and control traffic
and/or goods-transportation
Types of System-on-a-Chip
Designs
Silicon in 2010
Density AccessTime
(Gbits/cm2)
(ns)
Die Area:
2.5x2.5 cm
DRAM
8.5
10
Voltage:
0.6 V
DRAM (Logic)
2.5
10
Technology: 0.07 m
SRAM (Cache)
0.3
1.5
Density
Max. Ave. Power Clock Rate
(Mgates/cm2)
(W /cm2)
(GHz)
Custom
25
54
3
Std. Cell
10
27
1.5
Gate Array
5
18
1
Single-Mask GA
2.5
12.5
0.7
FPGA
0.4
4.5
0.25
Why Lower Power
• Technology direction
• Portable systems
– long battery life
Reduced
– light weight
voltage/power designs
– small form factor based on mature high
performance IC
• IC priority list
technology,
high
– power dissipation integration to minimize
– cost
size, cost, power, and
speed
– performance
Microprocessor Power
Dissipation
Power(W)
Alpha 21164
50
Alpha 21264
P III 500
45
P II 300
40
35
Alpha21064 200
30
25
P6 166
20
P5 66
15
P-PC604 133
10
i486 DX2 66
P-PC601 50
i486
DX25
i386 DX 16
i486 DX4 100
i286
i486 DX 50
P-PC750 400
5
1980
1985
1990
1995
2000
year
Levels for Low Power Design
Hardware-software partitioning,
Power down
Complexity,
Concurrency, Locality,
Algorithm
Regularity, Data representation
Parallelism, Pipelining, Signal correlations
Architecture
Instruction set selection, Data rep.
Circuit/Logic
Sizing, Logic Style, Logic Design
System
Technology
Threshold Reduction, Scaling, Advanced packaging
SOI
Possible Power Savings at Different Design Levels
Level of
Abstraction
Algorithm
Expected Saving
Architecture
10 - 90%
Logic Level
Layout Level
20 - 40%
Device Level
10 - 30%
10 - 100 times
10 - 30%
Power-hungry Applications
• Signal Compression: HDTV Standard,
ADPCM, Vector Quantization, H.263, 2-D
motion estimation, MPEG-2 storage
management
• Digital Communications: Shaping Filters,
Equalizers, Viterbi decoders, Reed-Solomon
decoders
New Computing Platforms
P  kCFV
2
• SOC power efficiency more than
10GOPs/w
– Higher On Chip System Integration: COTS:
100W, SOAC:10W (inter-chip capacitive loads,
I/O buffers)
– Speed & Performance: shorter
interconnection,fewer drivers,faster
devices,more efficient processing artchitectures
• Mixed signal systems
Physical gap
• Timing closure problem: layout-driven logic and
RT-level synthesis
• Energy efficiency requires locality of computation
and storage: match for stream-based data
processing of speech,images, and multimediasystem packets.
• Next generation SOC designers must bridge the
architectural gap b/w system specification and
Low Power Design Flow I
Function
Partitioning and
HW/SW Allocation
System
Level
Specification
System-Level
Power Analysis
Behavioral
Description
Software
Functions
Power-driven
Behavioral
Transformation
Processor
Selection
Behavioral-Level
Power Analysis
Power Conscious
Behavioral
Description
Software-Level
Power Analysis
Software
Optimization
High-Level
Synthesis and
Optimization
To RT-Level Design
RT-Level
Power Analysis
Low Power Design Flow II
RT-level
Description
Data-path
RTL
Library
RTL
mapping
Controller
Logic Synthesis
and
Optimization
Gate-Level
Power Analysis
Gate-level
Description
Processor
Control and
Steering Logic
Memory
RTL
Macrocells
Standard cell
Library
High-Level
Synthesis and
Optimization
Switch-level
Description
Switch-Level
Power Analysis
Three Factors affecting Energy
– Reducing waste by Hardware Simplification:
redundant h/w extraction, Locality of
reference,Demand-driven / Data-driven
computation,Application-specific
processing,Preservation of data correlations,
Distributed processing
– All in one Approach(SOC): I/O pin and buffer
reduction
– Voltage Reducible Hardwares
– 2-D pipelining (systolic arrays)
– SIMD:Parallel Processing:useful for data w/
Example 1: Filter: Eliminating
Redundant Computations
Example2: IBM’s PowerPC
Lower Power Architecture
• Optimum Supply Voltage through Hardware Parallel,
Pipelining ,Parallel instruction execution
– 603e executes five instruction in parallel (IU, FPU, BPU, LSU,
SRU)
– FPU is pipelined so a multiply-add instruction can be issued
every clock cycle
– Low power 3.3-volt design
• Use small complex instruction with smaller instruction length
– IBM’s PowerPC 603e is RISC
• Superscalar: CPI < 1
– 603e issues as many as three instructions per cycle
• Low Power Management
– 603e provides four software controllable power-saving modes.
Power-Down Techniques
◆ Lowering the
voltage along with
the clock
actually alters the
energy-per-operation
of the
microprocessor,
reducing the energy
required to perform a
fixed amount of work
Voltage vs Delay
•Use Variable Voltage Scaling or Scheduling for Real-time
Processing
•Use architecture optimization to compensate for slower operation,
e.g., Parallel Processing and Pipelining for concurrent increasing
and critical path reducing.
Low Voltage Main Memories
Why Copper Processor?
• Motivation: Aluminum resists the flow of
electricity as wires are made thinner and
narrower.
• Performance: 40% speed-up
• Cost: 30% less expensive
• Power: Less power from batteries
• Chip Size: 60% smaller than Aluminum
chip
Silicon-on-Insulator
• How Does SOI Reduce Capacitance ?
Eliminated junction capacitance by using
SOI (similar to glass) is placed between the
impuritis and the silicon substrate
high performance, low power, low soft error
SOC Co-Design Challenges
• Current systems are complex and
heterogenous Contain many different types
of components
• Half of the chip can be filled with 200 lowpower, RISC-like processors (ASIP)
interconnected by field-programmable
buses, embedded in 20Mbytes of distributed
DRAM and flash memory, Another Half:
ASIC
Configurability
• One-M gate reconfigurable, one-M gate
hardwired logic.
• 50GIPS for programmable components or
500 GIPS for dedicated hardwares
• Reduce design risks for which NRE costs
will become dominant
• 1 V with the watt range
Bridging the architectural gap
• Product reliability: design at a level far
above the RT level, with reuse factors in
excess of 100
• Trade-off: 100MOPs/watt (microprocessor)
100GOPs/watt (hardwired) Reconf.
Computing with a large number of
computing nodes and a very restricted
instruction set (Pleiades)
Implementing Digital
Systems
SOC CAD Companies
• Avant!
www.avanticorp.com
• Cadence
www.cadence.com
• Duet Tech
www.duettech.com
• Escalade
www.escalade.com
• Logic visions
www.logicvision.com
• Mentor Graphics
www.mentor.com
• Palmchip
• Synopsys
www.synopsys.com
• Topdown design solutions
www.topdown.com
• Xynetix Design Systems
www.xynetix.com
• Zuken-Redac
www.redac.co.uk