Transcript Reconfigurable Devices

Reconfigurable
Devices
Presentation for Advanced Digital
Electronics (ECNG3011)
by Calixte George
A Exponential History
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Long History in Digital Electronics from SSI to
MSI and now VLSI
Traditional Computer Architecture based on
Harvard & Von Neumann, using a processor
core and Instruction Set
Introduction of CPLD & then FPGAs
No. of transistors per unit die doubles every 18
months, leading to more dense FPGAs
ASICs & Applications on FPGAs
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Application Specific Integrated Circuits – very
expensive and rigid.
FPGAs – reconfigurable devices which utilize
CLBs and memory to organize a flexible array.
Reconfigurable devices have no limit to the
number of times they can be changed – true
firmware.
Immediate application in testing &
experimentation in R&D.
Traditional Uses vs. Future
FPGAs “traditionally” used in development
of systems to be rendered onto PCBs.
 Originally Popular in educational aspects
of Digital Electronics
 Could there be a greater application?
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 How
about many ASICs on one FPGA?
 How about reconfigurable computing?
Experimental Use-specific
Applications
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In the first half of the 1990s experimental boards were
used to accelerate a collection of applications, including
genome (DNA) pattern matching, determining stereo
vision from paired images, human fingerprint minutia
matching, solving three-dimensional heat equations, and
Hough transforms and Gaussian/Laplacian pyramid
generation for images.
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These used a combination of 16 FPGA cores
interconnected.
Adaptive Computing
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It is immediately obvious that a custom built circuit would
operate much faster than a traditional computer system
that requires running a programme on a generic device
with various shared functions.
Development of cores for different computer
applications.
Development of a dynamic computer that reconfigures
its resources. It would have a memory of stored designs
and reconfigures its gate resources to fit particular
requirements.
Issues in Development
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A well entrenched Computer Industry that makes
clear distinctions between hardware and
software.
Creation of new Architectures that allow for the
integration of reconfig. devices.
Rate of increase in transistor density in FPGAs.
Layouts of FPGAs (e.g. 80-90% of surface is
interconnects; maximizing use of LUTs?)
Advantages of FPGAs
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Share flexibility and ease of development through HDLs.
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Ability to have a wide body of developers (digital design
equiv. of Linux in OS).
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Ability to perform operations repetitive operations much
faster than traditional μPs. (NB: rare operations not so
well). The familiar 90-10 rule asserts that 90% of
execution time is consumed by about 10% of a
program's code, that 10% generally being inner loops.
How to Converge?
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The development of Compilers
where users will code in a
software language (e.g. C) and
realize an instantiation at the
FPGA level.
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Meshing of FPGAs and
existing uPs so as to give
reconfigurable devices
particular tasks which require
heavy repetition (Hybrid
model).
Research Areas
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“Reconfigurable devices may do well with small, highly repetitious kernels in
applications, but standard processors are still superior for the remaining
code that is irregular and/or rarely repeated.”
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For reconfigurable computing to be economically viable for more than a
small fraction of the market, the number of parts involved has to be
squeezed down to at most one chip, and preferably less. Existing
microprocessors are implemented in a single chip, and the pressure in the
market is always for fewer parts, not more.
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Reconfigurable hardware will not meet its full potential unless
reconfiguration time is minimized and the reconfigurable hardware also has
access to the computer's memory that is at least as good as that available
to the main processor.
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To better integrate a reconfigurable device into a computer, various
researchers have called for combining a traditional microprocessor with an
FPGA-like device onto one die to form a new kind of processor.
From FPGA to Microprocessor
References
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Augmenting a Microprocessor with
Reconfigurable Hardware, Hauser J R, UCBerkeley, 2000.
Balancing Interconnect and Computation in a
Reconfigurable Computing Array, DeHon A, UCBerkeley, 1999.
Automatic Compilation of C for Hybrid
Reconfigurable Architectures, Callahan T J, UCBerkeley, 2002.
FPGAs & Reconfigurable
Devices - A Slow
Revolution?
Thank you
September 26, 2005.