Transcript Intro-to-SOC-platform..

Module2: Introduction
to SOC design
최해욱 (ICU, 공학부)
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) 목차

System-on-Chip Architectures

SoC Design Methodology

Platform-based Design

Configurable Processor Cores
Copyrightⓒ2003
2
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
‘Top Ten Obstacles to 3G
Wireless Technology’
from: Carl Panasik “Overcoming Obstacles to 3G Wireless Technology”, Communications Syst
em Design, January, 2001, pp. 11-12.. Reused with permission.
Carl Panasik is in the Wireless Unit of TI.
 Stable
Standards
 Increased DSP Performance
 Software Sophistication
 Lower Power Consumption
 Advanced Power Management
 Increased Battery Capacity
 3G OSes
 Enhanced Radio Technology
 Cost Concerns
 Innovative Applications
Copyrightⓒ2003
3
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Shannon Beats More
1M
Algorithmic Complexity
(Shannon’s Law)
1000 x
2x/3-6 months
10,000
100
2x/18 months
97
99
‘01
‘03
‘05
Processor
Performance
(~Moore’s Law)
2016: 2500 MIPS
‘07
(Source: MorphICs)
Copyrightⓒ2003
4
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Technology Roadmap
시장전망 (단말기)
3.5G
밴드폭
2GHz
속도
3-6Ghz
14.4Mbps
다운로드
100 Mbps
10MB/200sec
Image Bit Rate
385kbps
350,000
4G
100MB/10sec
24MbpsX2
Revenue(million $)
3G
300,000
250,000
200,000
150,000
100,000
에너지 소모량
30-50W
175W
0
2000
Contents
700kbytes
CPU
800 Mhz
집적도
1999
15Mbytes
Copyrightⓒ2003
2003
2005
개인화:
고속화:
저전력화:
재사용화:
2002
2003
2007
2004
2005
2006
Year
5-10GHz
200M gates
2001
2001
*출처 ETRI, 2000
1B gates
2010
Context-aware Sensor Networks
NoC 기술
ACM, PSM, DVS, GC, LCC
Hardware/Software Co-design
5
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Implementation Choices for
a 3G Device
Cadence
What is my IP supplier
chain process?
What IP do I build,
what IP do I buy?
What do I reuse?
Image processing
RISC/DSP/ASIC
Sensor
A/D
How can I use
IP standards?
Pixel Defect Masking
Demosaic, Gamma
RGB-YUV, JPEG
I/O & Network Stack
SRAM/DRAM/Flash
MEMORY
Mic
A/D
Amp
Photo MEMORY
Flash
Multilevel Flash
Disk, DVD
Copyrightⓒ2003
How do I reuse
my own IP?
If I change
architecture, what
happens to
performance?
What
functions
What information is
do I
required to integrate IP?
integrate?
I/O Channels
Does the IP integrate
throughout the flow?
USB Node
Blue Tooth
1394/FireWire
V.90 Modem
ETHERNET
I/O
Will this
platform
meet cost
targets?
PCI
RISC/DSP/ASIC
G.723.1/ADPCM
Audio Compression
Video/Ch3 RF
MEMORY
3G WCDMA
BATTERY
RF WIRELESS
CHARGER/PWR MGMT
IrDA
UNTETHERED CAMERA
View Finder
LCD Display
6
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) System-on-Chip Architectures

A system-on-chip architecture integrates several
heterogeneous components on a single chip
Memory
Microcontroller
AnalogDigital
Communication
Structure
DSP


FPGA
DigitalAnalog
Custom
Hardware
Increasingly powerful applications are possible!
An efficient implementation requires many low
level details
Copyrightⓒ2003
7
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) A typical system-on-chip

A typical system-on-chip on a single chip
Memory
Micro-processor
Custom
Logic
(ASIC)
DSP
I/O
System on a chip
Copyrightⓒ2003
8
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform

Canonical form of an SoC








A microprocessor and its
memory subsystem
On-Chip buses
A memory controller for external
memory
A communications controller
A video decoder
A timer and interrupt controller
A general purpose I/O (GPIO)
interface
A UART interface
Memory
MicroProcessor
I/O
Control
BUS
BRIDGE
Video
Decoder
Memory
Ctrl
TIMER
GPIO
INTR
CTRL
UART
DRAM
Copyrightⓒ2003
9
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) SoC Architectures

A SoC integrates many heterogeneous
components on a single chip

A SoC is a parallel architecture and thus the
work on parallel computers can be used

A key challenge is to design the
communication between the different entities
of a SoC in order to minimize the
communication overhead
Copyrightⓒ2003
10
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Structured SoC Designs




Hierarchy: Subdivide the design into many levels of
sub-modules
Regularity: Subdivide to max number of similar submodules at each level
Modularity: Define sub-modules unambiguously & well
defined interfaces
Locality: Max local connections, keeping critical paths
within module boundaries
Copyrightⓒ2003
11
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) How to design future embedded systems?

Specification

Idea
abstract
(Specification)
Design
o Design productivity increases with the level of
abstraction
o The task of functional verification is very difficult
at low abstraction levels
Abstraction
Gap
Implementation
o Efficient implementations require to exploit the
low-level features of the target architecture
detailed
Product
(Implementation)
Challenge for
System Design!
Copyrightⓒ2003
12
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Abstraction Levels
SYSTEM
CHIP
REGISTER
GATE
CIRCUIT
SILICON
It is important to work on the right level of abstraction!
Copyrightⓒ2003
13
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Circular Y-Chart
Copyrightⓒ2003
14
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Common Fabric for IP
Blocks




Soft IP blocks are portable, but not as predictable as
hard IP.
Hard IP blocks are very predictable since a specific
physical implementation can be characterized, but are
hard to port since are often tied to a specific process.
Common fabric is required for both portability and
predictability.
Wide availability: Cell Based Array, metal
programmable architecture that provides the
performance of a standard cell and is optimized for
synthesis.
Copyrightⓒ2003
15
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) System Level
IMU
A/B
Computer
Radar
C/D
IMU: Interrupt Managing Unit (?)
C/D: Carrier Detection (?)
Copyrightⓒ2003
16
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Chip Level
RAM
16
uP
Pararllel
Port
8
USART
Interrupt
Controller
Copyrightⓒ2003
17
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Register Level
Sel
Reg
MUX
Clk A
Reg
Clk B
Inc
Copyrightⓒ2003
18
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Gate Level
Cout
A
P
Sum
B
Cin
Copyrightⓒ2003
19
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Transistor Level
Vdd
GP
SP
DP
Vout
Vin
DN
GN
SN
GND
Copyrightⓒ2003
20
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Layout (Silicon) Level
Vin
GND
Vdd
Vout
Copyrightⓒ2003
21
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) The importance of the level of abstraction

The right level of abstraction allows to make the
appropriate decisions without considering
unnecessary details

Shorter design times

Though in theory everything can be fine-tuned at
the silicon level, it is in practice impossible to
make a large design at the silicon level
Copyrightⓒ2003
22
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) SoC Design


The continuous progress in silicon process
technology allows to increase more and more
functionality on a single chip => Systems on a
chip become reality
Market-driven forces:
o Shorter product design schedules and life spans
o Products have to confirm to standards
o The design has to be right from the start. An
implementation error means heavy loss of money or
product death
o Large designs are integrated into a single chip

The SoC design process must address these
driving forces
Copyrightⓒ2003
23
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Primary Design Methodologies

Area Driven Design (ADD)
o Digital ASIC on older process technologies

Timing-Driven Design (TDD)
o Digital ASIC on Deep Submicron (DSM)

Block-Based Design (BBD)
o Complex ASIC with Intellectual Property Blocks

Platform-Based Design (PBD)
o System-on-a-chip
Copyrightⓒ2003
24
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Area-Driven Design (ADD)

Earlier process technologies were not able to
integrate very many transistors on a single chip

Area was very important and the effort was put on
logic optimization

ADD was used mainly for new designs (no reuse)
Logic
Copyrightⓒ2003
25
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Timing-Driven Design (TDD)

With continuous improvements in process
technologies, area became less important

Focus shifted to performance (speed and power)
constraints

Time-to-market became increasingly important

TDD is used for new designs on DSM processes

Design teams are small
Logic
Copyrightⓒ2003
26
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Timing-Driven Design (TDD)

TDD became possible due to:
o Interactive floor-planning tools, which gave good area and
delay estimates
o Static-timing analysis tools, which inform the designer, if
timing requirements are violated
o Compiler (synthesis) tools, which move the design to
higher levels of abstraction
Copyrightⓒ2003
27
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)




Improved process technologies allow to put
additional components on a single chip (memory,
microprocessor cores)
Applications are more complex and are very difficult
to design and verify, if developed from scratch
Multiple design teams work on different parts of the
system
Reusable virtual components (VCs) can be acquired
from other companies
Copyrightⓒ2003
DSP Core
Memory
IP-Block
Logic
Complex ASIC
28
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)




Ideally a BBD is behaviorally modeled at the system
level
HW/SW trade-offs, functional HW/SW co-verification
is ideally performed at that level
Design is partitioned into several components, which
are then designed at a lower level (RTL for HW)
Then the entire design is verified (integration test)
Copyrightⓒ2003
29
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)
System
Model
Partitioning
& Mapping
HW-Model
(VHDL)
SW-Model
(C/C++)
HW
Synthesis
SW
Compilation
Netlist
Copyrightⓒ2003
Verification
Executable
Program
30
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Block-Based Design (BBD)

BBD has been possible due to:
o High-level system analysis tools
o Block floor planning
• Constraint budgets for top-level chip interconnects
• Infrastructure models for clock, test, and bus architectures
that can be used for timing abstraction
o Integrated synthesis and physical design
• The influence of physical design issues is handled in the
synthesis process (better tools)
Copyrightⓒ2003
31
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Platform-Based Design (PBD)



Deep Submicron Technologies allow to put many
components on a single chip
The costs for test and verification are continuously
increasing
Design Reuse is a prerequisite to enable PBD and
shortens Time-To-Market
ATM
RAM
MPEG
ROM
DSP Core
Proc Core
System-on-a-Chip
Logic
Copyrightⓒ2003
32
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Platform-Based Design (PBD)




Like BBD, PBD starts at System Level (similar design flow)
PBD is heavily based on design reuse
Pre-verified blocks with standardized interfaces are used
The following design concepts must be further developed:
o Interface Standardization
o Virtual Component Design


Objective: Plug & Play Design
Important: Standardized Test Strategies that can be used
for systems consisting of several components
Copyrightⓒ2003
33
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈2) Platform-Based Design (PBD)

PBD becomes possible due to
o System-level and architectural design tools and methodologies
o Physical Layout Tools
• Bus planning
• Block Integration
o Virtual Components functional verification tools

There is a key problem with Virtual Components
(IP-blocks): IP-vendors do not want to reveal the internal
secrets of their designs!
Copyrightⓒ2003
34
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
SoC Platform의 종류
􀂉 The SoC platform consists of
o A library of hardware components
o An architecture for their interconnection
􀂉 The Application Platform (예: the OMAP product)
o Processor and Peripherals
o Low-Level Software (Drivers)
o Development Environment
􀂉 The System Platform
o The platform includes the code that controls all
aspects of the system from device driver to system
interface
Copyrightⓒ2003
35
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
OMAP: Hierarchy of Platforms
Copyrightⓒ2003
36
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Digital ASIC Design
􀂉 ASIC = Application Specific Integrated Circuit
􀂉 An ASIC is an integrated circuit for a
specifc application and (generally) produced in
relatively small volumes.
􀂉 An ASIC-technology helps to shorten the design
time by providing a semi-fabricated integrated
circuit
Copyrightⓒ2003
37
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Microprocessor
􀂉 A microprocessor can be used to implement
combinational and sequential functions
􀂉 Microprocessors have a large overhead in form of
logic that is needed to implement the functionality of
the microprocessor
􀂉 Microprocessors are slow compared to customized
hardware
􀂉 Application specific specific microprocessors
do exist, e.g. DSPs
Copyrightⓒ2003
38
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
ASIC Family
The term ASIC is often reserved for circuits that are
fabricated in a silicon foundry, while circuits that can
be programmed at the customer’s site are called
 Programmable Logic.

􀂉
􀂉
􀂉
􀂉
Programmable Logic Device (PLD)
Field Programmable Gate Array
Standard Cell
Gate Array
The term full custom is reserved for circuits where all
silicon layers can be optimized. This implies a long
design process and thus full custom is mainly used for
high-volume high-end circuits.

Copyrightⓒ2003
39
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
STD Cell and Gate Array
Standard cells are often referred as Cell-Based
Integrated Circuits (CBIC)
􀂉 All mask layers are customized
􀂉 The standard cell library defines logic elements of
varying complexity: SSI, MSI logic, data path
blocks, memories and system-level blocks.
􀂉A gate array chip contains prefabricated adjacent rows of
PMOS and NMOS transistors
􀂉 The gate array is configured by the interconnect
structure
Copyrightⓒ2003
40
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
FPGA
􀂉 None of the layers is
customized
􀂉 Basic logic cells and
interconnect can be
programmed
􀂉 Basic cells can be
SRAM based, Flash
Memory based or
fuse-based (one time
programmable)
Copyrightⓒ2003
41
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Comparison FPGA, Gate Array,
Standard Cell
Copyrightⓒ2003
42
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
Design Trade-Off
Copyrightⓒ2003
43
Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform
(모듈) 참고문헌




“System Modeling – Model of Computation and their Applications,” Axel
Jantsch LECS, Royal Institute of Technology, Stockholm, Sweden Jan,
2004.
“Winning the SoC Revolution-Experiences in Real Design,” Grant Martin
& Henry Chang, Cadence Labs, KAP, Jun, 2003.
“System Design and Methodology: Modeling and Design of Embedded
Systems,” Petru Eles, Linkopings Univ., Sweden
“Memory Issues in Embedded Systems-on-Chip,” Preeti Ranjan Panda
(Synopsys, Inc.), Nikil Dutt (Univ. of Cal/Irvine), Alexandru Nicolau
(Univ. of Cal/Irvine), KAP 1999.
Copyrightⓒ2003
44