Transcript Sunil`s presentation - Dept. of Electrical and Computer Engineering

A modified Scan Flipflop Design to
Reduce Test Power
Sivakumar Ganesan
Sunil P Khatri
Department of Electrical and Computer
Engineering
Texas A&M University
College Station, TX
1
Outline
 Scan based Testing.
 Impact of Test power.
 Switching power
 Leakage power.
 Previous work on Flip-flip modification to
reduce test power.
 Proposed Flip-flop.
 Experimental results.
 Conclusion.
2
Scan based Testing
Primary
Primary
Inputs Combinational Outputs
Logic
Di
FF
Qi
Clk
•
FFs
Primary
Primary•
Combinational Outputs
Inputs
Logic
Scan
Data
Out
FFs
Transform flip-flops
in the design into a
shift register chain
In “scan” mode, we
can now
• Shift in test vectors
• Shift out test
response
Regular Flip-flop
Di
00
11
Qi-1
Scan Clk
Mode
Qi
FF
Scanned Flip-flop
Scan Data In
3
Scan based Testing
 Benefits
Adds delay in the functional path
2. Requires additional input signals
 Transforms a sequential
design into a combinational
design for testing purposes
 Significantly simplifies the
test problem
 Enables at-speed testing as
well.
 Drawbacks
 Requires more signals to be
routed in the chip, and also
more pins on the package
 Adds extra delay in the
functional path.
4
Test time Calculation
 A test pattern consist of N shift cycles + 1
capture cycle (here N = number of flip-flops in
a scan chain.)
 If there were a total of P patterns to test the
design, this would require N*P shift cycles + P
capture cycles.
 Test time is directly proportional to the N*P and
inversely proportional to the frequency of the
shift clock.
 The shift frequency is limited by
 Tester hardware
 Power dissipation
5
Source of Power Dissipation
 Dynamic Power
 Historically dominated power
in CMOS
 Caused by signal switching
 Pdyn = C V2 f
 Leakage power
 Non-issue a few process
generations ago
 Exponential increase with
decreasing VT
 Dominates power in recent
generations
 Any power reduction
approach must address both
6
Power Dissipation during
Scan Testing
 Dynamic power
 The majority of dynamic power is consumed by the flip-flop
outputs (which drive the combinational logic) switching during
serial shift.
 Combinational logic can switch during each cycle of the scan
clock.
 Can be eliminated by ensuring that the combinational inputs do not
switch during scan
 Leakage power
 Suppose combinational inputs do not change during scan
 Leakage can be minimized by “parking” the combination logic in a
low-leakage input state.
 Typically, the leakage of a circuit can vary by a factor of 2,
depending on the input state of the circuit.
 Our solution addresses both types of power consumption
7
Previous Work – Latch
based approach
o In normal mode, the
“master” and the
“additional slave” latches
form the flip-flop.
=0
1
 In scan mode, the
“additional slave” latch is
disabled, the “master” and
“slave” latches form the flipflop
 The Q signal going to the
combinational logic does not
change, thereby reducing
dynamic power during scan
shifting
8
Previous Work – AND gate
approach
o In normal mode, QEN=1,
and Q, QZ follows the
flip-flop output Q1.
o SQ, the scan data output
signal, also follows Q
=1
=0
o In scan mode, QEN=0, so
Q, QZ are held constant at
‘0’ and ‘1’ respectively.
o SQ switches as required.
o Hence the inputs to the
combinational logic do not
change, reducing dynamic 9
power during scan shifting
Proposed Scheme – Flipflop1
SE
SE
• In normal mode, SE=0 and Q
as driven by the output of the
DFF (Q1)
• PMOS device P1 is turned off.
P1
D
Din
Q1
Q
SD
SE
CLK
SQ
• In scan mode, SE=1, so the
PMOS device P1 turns on, and
Q is statically 1.
• Hence the combinational logic
does not switch, resulting in a
reduction in dynamic power
during scan shifting
• SQ, the scan data output, also
follows the output of the DFF
and drives the next flip-flop in
the scan chain.
10
Proposed Scheme – Flipflop0
SE
D
Din
Q1
SD
SE
SE
CLK
• So, by using Flipflop0 or
• In normal mode, SE=0 and Q
Flipflop1, we have the same
as driven by the output of the
operation in normal mode
DFF (Q1)
• But Flipflop0 has a static 0
• NMOS device N1 is turned off.
output in scan mode, while
Q Flipflop1 has a static 1 output
In scan mode,
SE=1,
so the
•• Suppose
leakage
is minimized
NMOS
N1 turns on,
and
N1
when
thedevice
combinational
inputs
Q isinstatically
0. state S.
are
a particular
Hence
the combinational
logic
•• We
choose
between Flipflop0
does
not switch,
resulting
in a
or
Flipflop1
for each
memory
SQ reduction in dynamic power
element, so that combinational
duringare
scan
inputs
inshifting
state S, in scan
• SQ, the scan data output, also
mode.
the output
of theleakage
DFF
•follows
We thereby
minimize
and drives
the as
next
flip-flop in
power
as well
dynamic
the scan chain.
power.
11
Advantages over Other
Schemes
 Allows us to minimize both leakage and dynamic
power
 Previous approaches only minimize dynamic power
 Leakage power is comparable to dynamic power in
recent processes.
 Just require 3 more transistors per flip-flop
 AND gate approach required an additional AND gate
 Latch based approach required additional latch.
12
Experimental Results
 We will first discuss the characterization of the
new flip-flops
 Flipflop1 and Flipflop0 simulated in SPICE
 Report delay overhead compared to
 Non-scanned flip-flop
 AND gate based approach
 Then we will discuss leakage improvements that
can be availed using this approach
 Leakage characterization of library gates
 Leakage characterization for benchmark designs
 Compared to AND gate based approach
13
Flipflop1 schematic
14
Flipflop1 SPICE Waveforms
15
Flipflop0 Schematic
16
Flipflop0 SPICE Waveforms
17
Delay overhead
DFF type
Clock-Q Delay
% increase
Normal DFF with
no gating
267 ps
0
AND gate based
flip-flop
297 ps
11.2%
Flipflop1
319 ps
19.5%
Flipflop0
310 ps
16.1%
Average Delay overhead compared to normal scan flip-flop = 17.8%
Average Delay overhead compared to AND gate approach = 6.6%
18
Experimental Results
 Standard cells are characterized and their leakage
power is calculated for all input vectors
 The cells we use are NAND2, NOR2, INV, implemented in a
65nm process
 We mapped several benchmarks using these cells
 The leakage power consumption is calculated for
these benchmark combinational designs
 For the NAND gate based approach
 For our approach
 We assume that the inputs of the combinational logic
are driven by the scan flip-flop
 For our design, we choose Flipflop0 or Flipflop1 in a
manner that minimizes leakage.
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Leakage Power of
Standard Cells
Input
0
1
Leakage (nW)
3.912
29.17
a) Inverter
Input
00
01
0
11
Leakage (nW)
0.93
10.5
3.96
61.7
b) NAND2
Input
00
01
0
11
Leakage (nW)
7.92
29.62
12.7
2.81
c) NOR2
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Experimental Results
 The leakage-minimizing vector for our approach
was determined by choosing the lowest leakage
vector among 10,000 randomly selected vectors.
 In our approach, this vector can be applied during scan
shifting, by appropriately using Flipflop0 and
Flipflop1.
 There are several approaches to deterministically
find the vector that minimizes the leakage power
of combinational circuits.


"A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational
Designs in the Presence of Random PVT Variations", Gulati, Jayakumar, Khatri, Walker.
Integration, the VLSI Journal.
Several other competitive approaches exist as well.
21
Experimental results
Design
Leakage (AND gate
based) (nW)
Leakage (our approach)
(nW)
Improvement (%)
ALU2
5719
5333.6
6.7
apex6
12578
12578
0
apex7
3929
3818
2.8
C17
108
108
0
C432
4008.4
3370
15.9
C449
10966
10946
0.18
C880
7733
6445
16.6
C1355
10966
10946
0.18
C1908
10608
9554
9.9
C3540
26785
23057
13.9
C5315
39816
33397
16.1
C6288
64561
51808
19.7
C7552
46740
44684
4.3
Dalu
15165
13954
7.9
Decod
243.5
243.5
0
I1
787.1
549.6
30.1
I2
5094.9
1573.6
69.1
I3
1053
618.6
41.2
AVERAGE
14.1
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Conclusion
 We have presented an approach to reduce the total power
during scan based on the use of one of 2 scan flip-flops.
 Allows the designer to minimize dynamic power as well as
leakage power.
 Leakage power increases exponentially with newer technologies,
and is comparable to dynamic power in today’s designs.
 The approach reduces test power thereby
 Leading to increase in the test clock frequency
 Reducing test time and test cost as well.
 Requires the addition of three transistors per flip-flop
 Less expensive than approaches that target reduction of dynamic
power (alone)
 On average, leakage power reduced by ~14% using our
approach
 Results in a slight delay overhead of ~ 6.6% compared to
earlier schemes.
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