Transcript 2007_PCSI_rodwell_slides - Electrical and Computer Engineering

PCSI Conference, January 15, 2008, Santa Fe
THz & nm Transistor Electronics:
It's All About The Interfaces.
M. Rodwell, Art Gossard
University of California, Santa Barbara
Collaborators (III-V MOS)
A. Gossard, S. Stemmer, C. Van de Walle
University of California Santa Barbara
C. Palmstrøm,
University of Minnesota
P. Asbeck, A. Kummel, Y. Taur,
University of California San Diego
M. Fischetti
University of Massachusetts Amherst
J. Harris, P. McIntyre,
Stanford University
[email protected] 805-893-3244, 805-893-5705 fax
TeraHertz and nanoMeter Electron Devices
How do we make very fast electron devices ?
...by scaling
What are the limits to scaling ?
attainable contact resistivities,
attainable thermal resistivities
attainable contact stabilities
and for FETs, attainable capacitance densities
How can the materials growth community help ?
work on interfaces (contacts and gate dielectrics) !
Guidance of utility of other device structures / features
nanowire pillar devices
access resistances & capacitances
relevance and irrelevance of mobility
THz & nm
Semiconductor
Device Design...
... is scaling
Frequency Limits
and Scaling Laws
of (most)
Electron Devices
PIN photodiode
Rtop
  thickness
C  area / thickness
Rtop   contact / area
Rbottom
Rbottom  1 / stripe length
I max, space-charge-limit  area / thickness

2
power
 length 
T 
 log 

length
 width 
To double bandwidth,
reduce thicknesses 2:1
reduce width 4:1, keep constant length
current density has increased 4:1
resistance
capacitance
transit time
device bandwidth
Rtop
Rbottom
applies to almost all semiconductor devices:
transistors: BJTs & HBTs, MOSFETS & HEMTs,
Schottky diodes, photodiodes, photo mixers, RTDs,
...
high current density,
low resistivity contacts,
epitaxial & lithographic scaling
FETs only: high ereo/D dielectrics
THz
semiconductor
devices
Why aren't semiconductor lasers R/C/ limited ?
+V (DC)
metal
P+
P-
high er
I
optical
mode
AC output
field
NN+
metal
-V (DC)
dielectric waveguide mode confines AC field
away from resistive bulk and contact regions.
AC signal is not coupled through electrical contacts
dielectric mode confinement is harder at lower frequencies
Bipolar Transistor Design
Bipolar Transistor Design is Simple
We
 b  T 2 Dn
2
b
Tb
 c  Tc 2v sat
Rex  contact /Ae
 We Wbc  contact
 
Rbb  sheet 

 12 Le 6 Le  Acontacts
emitter
Ccb  eAc /Tc
I c, Kirk  vsat Ae (Vce,operating  Vce,punch-through) / T
2
c
P
T 
LE

 Le 
1  ln  
 We 

Wbc
Tc
length LE 
HBT scaling laws
Goal: double transistor bandwidth when used in any circuit
→ keep constant all resistances, voltages, currents
→ reduce 2:1 all capacitances and all transport delays
b  T
2
b
2 Dn  Tb / v
 c  Tc 2v
We
Tb
Wbc
Tc
→ thin base ~1.414:1
→ thin collector 2:1
Ccb  Ac /Tc → reduce junction areas 4:1
Rex   c /Ae → reduce emitter contact resistivity 4:1
I c, Kirk  Ae / Tc2 (current remains constant, as desired )
emitter
length LE 
need to reduce junction areas 4:1
 Le 
P


T 
ln

K InP LE  We  K InP LE reduce widths 2:1 & reduce length 2:1 → doubles T
reducing widths 4:1, keep constant length→ small T increase ✓
P
Rbb 
 sWe
12 Le

 sWbc
6 Le

c
Acontacts
→ reduce base contact resistivity 4:1
reduce widths 2:1 & reduce length 2:1 → constant Rbb ✓
reducing widths 4:1, keep constant length → reduced Rbb
✓✓
Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.
Bipolar Transistor Scaling Laws
Changes required to double transistor bandwidth:
parameter
collector depletion layer thickness
base thickness
emitter junction width
collector junction width
emitter contact resistance
current density
base contact resistivity
change
decrease 2:1
decrease
1.414:1
decrease 4:1
decrease 4:1
decrease 4:1
increase 4:1
decrease 4:1
Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.
Status of Bipolar Transistors : September 2007
200 GHz 300 GHz 400 GHz
500 GHz 600 GHz

popular metrics :
f or f max alone
f f max
800
Teledyne
250 nm
700
UIUC DHBT
NTT
f
max
(GHz)
600
UIUC SHBT
600nm
400
UCSB DHBT
NGST
300
Pohang
350 nm
200
HRL
IBM SiGe
100
Vitesse
Updated Sept. 2007
0
0
100
200
300
400
500
ft (GHz)
600
f f max
(1 f  1 f max ) 1
ETHZ/SFU
250 nm
500
( f  f max ) / 2
700
800
much better metrics :
power amplifiers :
PAE, associated gain,
mW/ m
low noise amplifiers :
Fmin , associated gain,
digital :
f clock , hence
(Ccb V / I c ),
( Rex I c / V ),
( Rbb I c / V ),
(τb  τc )
150 nm thick collector
256 nm Generation
InP DHBT
40
dB
H
mA/m2
10
30
U
21
20
fmax = 780 GHz
10

10
10
10
11
10
S11
12
11
10
2
= 560 GHz
15
10
5
10
10
11
10
0
12
10
1
2
V
Hz
260
280
300
freq. (GHz)
200 GHz
master-slave
latch design
30
H
320
21
30
U
2
240
4
40
mA/m
-20
220
3
ce
60 nm thick collector
from one HBT
S21
-15
5
0
0
9
10
dB
S21, S11, S22 (dB)
S22
-10
4

0
-5
3
20
f = 560 GHz
5
2
21
mA/m
dB
4.7 dB Gain at 306 GHz.
340 GHz, 70 mW amplifier design
10
max
1
V
U
f
0
12
10
ce
10
10
10
9
10
H
20
4
0
Hz
70 nm thick collector
30
6
2
f = 424 GHz
0
9
10
8
20
10 fmax = 218 GHz
20
10
f = 660 GHz
t
Z. Griffith, E. Lind,
J. Hacker, M. Jones
0
9
10
10
10
11
10
Hz
10
12
0
0
1
2
V
ce
3
InP Bipolar Transistor Scaling Roadmap
industry university university appears
→industry 2007-8
feasible
maybe
emitter 512
16
256
8
128
4
64
2
32 nm width
1 m2 access 
base
300
20
175
10
120
5
60
2.5
30 nm contact width,
1.25 m2 contact 
collector 150
4.5
4.9
106
9
4
75
18
3.3
53
36
2.75
37.5 nm thick,
72 mA/m2 current density
2-2.5 V, breakdown
520
850
430
240
730
1300
660
330
1000
2000
1000
480
1400 GHz
2800 GHz
1400 GHz
660 GHz
f
fmax
power amplifiers
digital 2:1 divider
370
490
245
150
How Can Material Scientists Help ?
To build a 5-THz bipolar Transistor...
...we need 0.25 -m2 Ohmic contacts,
& these must be stable at 300 mA/m2.
...Can you help ?
Ohmic Contacts
Ex-Situ Ohmic Contacts are a Mess
textbook contact
with surface oxide
with metal diffusion
Surface contaminated by semiconductor oxides
On InGaAs surface: Indium and Gallium Oxides, elemental As
Metals Interdiffuse with Semiconductor
TiPtAu contacts: Ti diffusion. Pt contacts: reaction. Pd contacts: reaction
Interface is degraded → poor conductivity
Interface is badly-controlled→ hard to understand→ hard to improve
Our HBT Base Contacts Today Use Pd or Pt to Penetrate Oxides
TEM : Lysczek, Robinson, & Mohney, Penn State
Sample: Urteaga, RSC
Pt
Reacted region
InGaAs
Pt Contact after 4hr 260C Anneal
Au
Wafer first cleaned in reducing
Pd & Pt react with III-V semiconductor
Penetrate surface oxide
Pt
Reacted region
InGaAs
Provide ~5 -m2 resistivity
(InGaAs base, 8*1019/cm3)
reaction depth is a problem for HBT base
Pt/Au Contact after 4hr 260C Anneal
Chor, E.F.; Zhang, D.; Gong, H.; Chong, W.K.; Ong, S.Y. Electrical characterization, metallurgical investigation, and thermal stability studies of (Pd, Ti, Au)-based ohmic contacts. Journal of Applied Physics, vol.87, (no.5), AIP, 1 March 2000. p.2437-44.
Improvements in HBT Emitter Access Resistance
U. Singisetti
A. Crook
S. Bank
E. Lind
125 nm generation requires 5  - μm2 emitter resistivities
65 nm generation requires 1-2  - μm2
Recent Results
ErAs/Mb
MBE in-situ
Mo
MBE in-situ
TiPdAu
ex-situ
TiW
ex-situ
J(mA/um^2)
Degeneracy contributes 1  - μm2
10
2
10
1
10
0
10
1.5  - μm2
0.6  - μm2
0.5  - μm2
0.7  - μm2
20 nm emitter-base depletion layer
contributes 1  - μm2 resistance
Te=0 nm
Fermi-Dirac
-1
10 nm steps
Boltzmann
10
-2
10
-3
-0.3
Equivalent series
resistance approximation
-0.2
-0.1
V -
be
0
0.1
0.2
E fn ( x)
x
J

qn( x)
Te=100 nm
In-situ ErAs-InGaAs Contacts
Epitaxially formed, no surface defects, no Fermi level pinning (?)
In-situ, no surface oxides, coherent interface, continuous As sublattice
J.D. Zimmerman et al., J. Vac. Sci. Technol. B, 2005
Thermodynamically stable
ErAs/InAs Fermi level should be above conduction band
1
InAlAs/InGaAs
Approximate Schottky barrier potential
III Er As
D. O. Klenov, Appl. Phys. Lett., 2005
Results nevertheless disappointing:
1.5  - μm2
S.R. Bank, NAMBE , 2006
Low-Resistance Refractory Contacts to N-InGaAs
Results initially by luck: control samples for ErAs experiments
Mo contacts: deposition by MBE immediately after InGaAs growth
TiW contacts: sputter deposition
after UV-Ozone & 14.8-normality ammonia soak
Both give ~ 1 -m2 resistitivity
in-situ Mo contact
ex-situ TiW contact
Coherent Epitaxial Metal Semiconductor Contacts ?
Chris Palmstrom suggests materials such as
Fe3Ga, CoGa, NiAl
It might be possible to grow these with low interfacial densities
on InGaAs or InAs.
Key question: what resistivity would we expect for a
zero-defect, zero-barrier metal-semiconductor interface ?
If we introduce a small difference in Fermi Level between metal
and semiconductor, what current do we compute from
integration of N(E) v(E)F(E)T(E) ?
Shape as Substitute for Low-Resistance Contacts: SiGe HBTs
wide emitter contact: low resistance
narrow emitter junction: scaling (low Rbb/Ae)
P base
thick extrinsic base : low resistance
thin intrinsic base: low transit time
wide base contacts: low resistance
narrow collector junction: low capacitance
SiO2
N+ subcollector
These are planar
approximations to
radial contacts:
→ reduced access resistance
N-
SiO2
extrinsic
emitter
extrinsic
base
2  bulk  2  r 

ln 

L
W


2
Rcontact  c
Lr
Rbulk 
extrinsic
base
N+
subcollector
should help less with small devices:
...widths scale faster than thicknesses→ trench fringing capacitance
dielectric trench conducts heat badly
Field-Effect Transistors
Simple FET Scaling
Goal double transistor bandwidth when used in any circuit
→ reduce 2:1 all capacitances and all transport delays
→ keep constant all resistances, voltages, currents
All lengths, widths,
thicknesses reduced 2:1
S/D contact resistivity reduced 4:1
C gs ~ eWg Lg / Tox
C gs, f ~ C gd ~ eWg
Csb ~ Cdb ~ eWg Lc / Tsub
If Tox cannot scale with gate length,
Cparasitic / Cgs increases,
gm / Wg does not increase
hence Cparasitic /gm does not scale
 ~ Lg / v
g m ~ C gs /  ~ (eLgWg / Tox ) / 
Gds ~ Cd ch /  ~ eWg / 
If Tox cannot scale with gate length,
Gds/gm increases
Well-Known: Si FETs no longer Scale Well
EOT is not scaling as 1/Lg
(ITRS roadmap copied from Larry Larson's files)
High-K gate dielectrics: often significant SiO2 interlayer, can limit EOT scaling
S/D access resistance also a challenge: about 1 -m2 required for 20 nm
Because gate equivalent thickness is not scaling, present devices scale badly
output conductance is degrading with scaling
other capacitances are not scaling in proportion to Cgs
hence are starting to dominate high frequency performance
How Can Materials Scientists Help ?
High K-dielectrics for Si CMOS are still extremely important
Self-aligned (Salicide-like) contacts
of very low resistivity are needed
...for 2 mA/micron operation at 700 mV gate overdrive,
we want ~300 Ohm-micron lateral access resistivity
→ about 0.7 Ohm-micron^2 resistivity in a 25 nm wide contact
Why consider III-V (InGaAs/InP) CMOS ?
Low access resistance: 1 -m2 , 10 -m
Light electron→ high electron velocity (thermal or Fermi injection)
→ increased Id / Wg at a given oxide thickness (?)
→ decreased Cgs /gm at a given gate length
Cox
Challenge:
Low density of states
Cdos
q 2 m*

 2
3.4 F/cm2
@ 1 nm EOT
Challenge:
filling of low-mobility
satellite valleys
limits ns to ~ 8*1012 /cm2
limits Id / Wg
Cdos
~3 F/cm2
ballistic case
limits ns to ~ 6*1012 /cm2
limits Id / Wg
limits gm /Wg
Challenge:
light electron limits vertical scaling
~1.5-2.5 nm minimum
mean electron depth
III-V MOS: What might be accomplished
Drive current
simulationideal (ballistic)
assumptions
r Composition
Optimization
for Highest
Ballistic Current
Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007
I_ballistic (mA/um)
7
50% InGaAs 50% InP
60% InGaAs 40% InP
40% InGaAs 60% InP
100% InGaAs
100% InP
6
5
4
3
2
implant
isolated
1
0
0
0.2
0.4
VG (V)
0.6
0.8
1
22 nmInGaAs:
gate length,
nm thick
InGaAs
/ InP
channel
• More
higher 5
injection
velocity,
lower
overall
mass
3-4 mA /m
intrinsic Cgs ~350 fF/mm --- comparable to fringing and stray capacitances
sical CMOS Research Center
er
well
sub-well
barrier
P+ InGaAs
Trade-offs between DOS and injection velocity:
• More
higher
overall mass,silicon
lower injection
velocity
underInP:
similar
assumptions,
channels
show
N+
N+
S/D Contact Process Flow For III-V MOSFETs
selective-area S/D regrowth
er
er
er
er
er
InGaAs well
er
well
er
well
er
well
InP well
InP well
InP well
InP well
barrier
(starting material)
barrier
barrier
CBE in-situ etch
barrier
CBE in-situ
selective-area regrowth
electroplate
S/D metal
non-selective-area S/D regrowth
er
er
er
er
er
er
er
InGaAs well
InP well
well
InP well
well
InP well
well
InP well
well
InP well
barrier
barrier
barrier
barrier
barrier
(starting material)
recess etch
nonselective regrowth
in-situ S/D metal
er
planarize
er
etch
er
strip planarization
material
III-V MOSFETs Can Provide Very Low S/D Access Resistance
Objective : I d /Wg ~ 5 mA/ m @ (Vgs  Vth )  0.7 V
 transcondu ctance g m / Wg  7 mS/ m
 14  - m source resistance will reduce g m and I d by 10%.
With 50 nm wide contacts, this requires  c  0.7  - m 2
L S/D
50 nm
Lg
sidewall
metal gate
T ox
source contact
N+ regrowth
gate
dielectric
drain contact
N+ regrowth
quantum well
barrier
undoped
substrate
P + substrate
Tw
undoped
substrate
Modern III - V HEMTs have ~ 10 : 1 larger (~ 100  - m) source resistance ...
because of the poor extrinsic source access region.
Improving FETs by Developing Other Materials
Other materials may offer high mobilities but...
ID
Id
increasing
VGS
VDS
Vgs
Vth
I D  coxWg vinjection(Vgs  Vth  V ) for (Vgs  Vth ) / V  1
where V  vinjectionLg / 
→ mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg
increased injection velocities are of value...
...but not at sacrifice in density of states
Nanopillar and Nanowire Devices
Nanopillar devices might have improved 2-D electrostatics
... but only if wire diameter is ~10 nm or less
Access resistances are serious issue
Capacitances to source-drain pad regions a serious concern
III-V Nanowires FETs still must address defect density
dielectric-semiconductor interface
III-V nanopillar devices experience same DOS, confinement
challenges as planar III-V devices
Conclusion
THz & nm Transistor Electronics is all about the interfaces
Bipolar Transistors:
P and N ohmic contacts with very low resistivity
stability at high current density
FETs
gate dielectrics
contact resistance
density of states