Transcript Title of Talk - University of California, Santa Barbara

2002 SSDM Conference, September, Nagoya
Submicron InP Bipolar Transistors:
Scaling Laws, Technology Roadmaps,
Advanced Fabrication Processes
Mark Rodwell
University of California, Santa Barbara
[email protected] 805-893-3244, 805-893-3262 fax
Applications of InP HBTs
Optical Fiber Transceivers
40 Gb:
InP and SiGe HBT both feasible
ICs now available; market has vanished
80 & 160 Gb may come in time
within feasibility for scaled InP HBT
world may not need capacity for some time
WDM might be better use of fiber bandwidth
1
mmWave Transmission
1 km
Sea level
60-80 GHz, 120-160 GHz, 220-300 GHz
Low atmospheric attenuation (weather permitting).
High antenna gains (short wavelengths).
10 Gb/s transmission over 500 meters with 20 cm
antennas needs 4 mW transmitter power
Mixed-Signal ICs for Military Radar/Comms
Log Transmission
0.1
0.01
1E-3
1E-4
1E-5
1E-6
0.0
0.2
0.4
0.6
Frequency, THz
direct digital frequency synthesis, ADCs, DACs
high resolution at very high bandwidths sought
0.8
1.0
How Do We Improve the Bandwidth of Bipolar Transistors ?
 kT

1
kT
  base   collector  C je
 Cbc 
 Rex  Rcoll 
2f
qI E
 qI E

Thinner base, thinner collector
 higher f , but higher RbbCcb , RexCcb …
what parameters are really important in HBTs ?
how do we improve HBT performance ?
How do we improve gate delay ?
Gate Delay Determined by :
Depletion capacitanc e charging
through the logic swing
 VLOGIC 

Ccb  Cbe,depletion 
 IC 
Depletion capacitanc e charging
through the base resistance
Rbb Ccb  Cbe,depletion 
Supplying base  collector
stored charge
through the base resistance
 IC 

Rbb  b   c 
 VLOGIC 
The logic swing must be at least
 kT

VLOGIC  6
 Rex I c 
 q

out
out
in
in
clock
clock
clock
clock
Delay not well correlated with f .
VLOGIC
I C Ccb  Cbe,depl  is 60% - 80% of total.
High I C / Ccb  is a key HBT design objective.
 Acollector  TC 





 Aemitter  2veffective 
Rex must be very low for low Vlogic at high J e
Ccb VLOGIC VLOGIC

IC
2VCE ,min
InP logic barely faster tha n SiGe :
need to design for clock speed, not f & f max
Scaling Laws for fast HBTs
Required proportion al change in HBT parameters in order to obtain
a  : 1 increase in bandwidth in an arbitrary circuit
For mesa HBTs, but not trans ferred - substrate or undercut - mesa HBTs,
the base contact resistivit y  v ( - cm 2 ) must also scale as  2
Challenges with Scaling:
Collector-base scaling
Mesa HBT: collector under base Ohmics.
Base Ohmics must be one transfer length → sets minimum size for collector
Solution: reduce base contact resistivity → narrower base contacts allowed
Solution: decouple base & collector dimensions
transferred-substrate, undercut-mesa, or buried SiO2 in junction (SiGe)
Emitter Ohmic Resistivity:
must improve in proportion to square of speed improvements
Current Density:
self-heating, current-induced dopant migration, dark-line defect formation
Loss of breakdown
avalanche Vbr never less than collector bandgap (1.12 V for Si, 1.4 V for InP)
….sufficient for logic, insufficient for power
Yield !
submicron HBT processes have progressively decreasing yield
Technology Roadmaps for 40 / 80 / 160 Gb/s
Low Ccb InP HBT structures
transferred-substrate
Allows deep submicron collector scaling
Problems with heating at high J
Low yield at deep submicron scaling
undercut-collector
emitter
base contact
undercut
collector junction
InGaAs
collector
InGaAs base
InP collector
collector
contact
Popular approach
Uncertain yield at submicron geometries
InGaAs subcollector
InP subcollector
SI substrate
Narrow-mesa with ~1E20 carbon-doped base
Conservative approach
Still not viable for > 3000 transistors per IC
Need improved device structures for high yield at 0.1 mm scaling
Miguel Urteaga
Unbounded Power Gain in Submicron InAlAs/InGaAs HBTs
Transistor Gains, dB
40
Emitter
30
unbounded U
U
0.3 x 18 mm2
U
20
MSG/MAG
Power gain is high,
but fmax can’t be determined
Collector
10
H
Ic = 5 mA,
Vce = 1.1 V
0
10
1 10
-14
8 10
21
0.7 x 18.6 mm2
100
Frequency, GHz
B12 /   Ccb  cancellati on terms
5 10
-3
-15
4 10
-3
-15
3 10
-3
6 10
2 10
-3
4 10
-15
1 10
-3
2 10
Ic = 1
Ic = 2
Ic = 3
Ic = 4
Ic = 5
-15
V =1.1 V
ce
0 10
mA
mA
mA
mA
mA
100
Frequency (GHz)
150
Ic = 1 mA
Ic = 2 mA
Ic = 3 mA
Ic = 4 mA
Ic = 5 mA
reduced
ce
0
60 mS=1/17k negative conductance at 110 GHz
-1 10
50
2
G12   2 C cbi
Rbb  negative G terms
V =1.2 V
0 10
0
0
Int. Symp. Compound Semiconductors, Tokyo, Oct. 2001
Int. Journal High Speed Electronics and Systems, to be published
1000
Gc (S)
Cc (Farads)
Unbounded 45-170 GHz
Unilateral power gain
200
-3
0
50
100
Frequency (GHz)
150
200
Capacitance modulation & negative resistance observed: Gunn-like or IMPATT effects ?
Miguel Urteaga
Collector velocity modulation: Ccb cancellation and negative resistance
 c  Tcoll / 2velectron  0.3 μm /( 2  3 105 cm/s )  0.5 ps
Ccbx
Ccbi
Ycb
Rbb
B
d 
 j c sin(  c ) 
 I C , DC  e

Ycb 
dVcb 
 c 
C
Cbe,depl
Ix
gmb
Rex
re=1/gm
 d  d  cos( c ) sin(  c ) 


Gcb  I C , DC  c  
 c
 dVcb  d c 


sin(  c ) 

I x  e  j c
 c 

1  d c  d  sin 2 ( c ) 



Ceq   I C , DC 
  dVcb  d c   c 
-3
2 10
-3
-3
cb
1 10
Real Part: Collector-Base Conductance
0 10
-1 10
0
-3
-2 10
-3
-3 10
-3
negative Ycb: 0-700 GHz
(340 mS=1/3000  at 120 GHz)
0
100
200
300
400
500
600
700
-Ic*d(tau_c)/dVcb= -Ccb,cancellation=-1 fF
3 10
equivalent capacitance, B / omega, Farads
collector-base conductance, Siemens
-Ic*d(tau_c)/dVcb= -Ccb,cancellation=-1 fF
E
1 10
-15
Equivalent Negative Capacitance, B /
cb
5 10
-16
0
-5 10
-16
-1 10
-15
equivalent negative Ccb:
starts decreasing at ~150 GHz
reaches zero at 370 GHz
0
100
200
300
400
500
Frequency, GHz
600
700
Frequency, GHz
If Ccb cancellation is observed, there must also be an associated negative resistance
2nd Hypothesis: weak IMPATT effects in the collector
 H  Tcoll / 2vhole  0.3 μm /( 2  5 10 4 cm/s )  3 ps
Ccbx
Ycb
Rbb
C
gmb
re=1/gm
Rex
IMPATT conductance, Siemens
-Ic*d(tau_c)/dVcb= -Ccb,cancellation=-1 fF
E
Again : Ccb  A Tc   I c  total Vcb  at low frequencie s
-4
Real Part: Collector-Base Conductance
3 10
-4
2 10
-4
1 10
-4
0 10
-1 10
negative conductance: 83-166 GHz
(70 mS=1/14,000  at 120 GHz)
0
-4
0
50
100
150
Frequency, GHz
200
250
cb
Ix

sin(  c ) 
sin(  H ) 
1  Me  j H

I x  e  j c
 c 
 H 

-Ic*d(tau_c)/dVcb= -Ccb,cancellation=-1 fF
Cbe,depl
4 10
 dM   j h sin(  H )
e
Ycb  I C , DC 
 H
 dVcb 
MPATT capacitance, B / omega, Farads
Ccbi
B
Miguel Urteaga
4 10
-16
2 10
-16
Equivalent Negative Capacitance, B /
12
0
-2 10
-16
-4 10
-16
-6 10
-16
-8 10
-16
-1 10
-15
equivalent negative Ccb:
starts decreasing at ~50 GHz
reaches zero at 166 GHz
0
50
100
150
Frequency, GHz
200
IMPATT effect also produces both capacitance cancellation and negative resistance
250
Deep Submicron Bipolar Transistors
for 140-220 GHz Amplification
Transistor Gains, dB
30
unbounded U
U
U
20
MSG/MAG
10
H
21
0
10
100
1000
Frequency, GHz
8
6
4
S21, dB
Miguel Urteaga
raw 0.3 mm transistor: 6-11 dB power gain @ 200 GHz
40
2
-2
1-transistor amplifier:
6.3dB @ 175 GHz
-4
140
150
0
160
170
180
190
200
210
220
Frequency, GHz
10
gain, dB
UCSB
0
-10
-20
-30
140
3-transistor amplifier:
8 dB @ 195 GHz
150
160
170
180
190
Frequency (GHz)
200
210
220
Mattias Dahlstrom (UCSB) Amy Liu (IQE)
Wideband Mesa InP/InGaAs/InP DHBTs
30
500 Ohm/square base sheet resistance
Pd/Ti/Pd/Au base Ohmic contacts
< 10-7 Ohm-cm2 base contact resistance
1 mm base contacts,
0.5 mm emitter junction
0.7 mm emitter contact
25
21
Gain (dB) H , U
2000 Å InP collector
300 Å InGaAs base
8E19 to 5E19 graded C base doping
InAlAs/InGaAs base-collector grade.
UCSB / IQE
20
282 GHz f
>450 GHz fmax,
15
480 GHz
10
5
Vce=1.7 V
J=3.7E5 A/cm2
0
7.5 V Breakdown
282 GHz f , > 450 GHz fmax ,
operation to 500 kA/cm2 at 1.7 volts
Rbb is low, Ccb needs further reduction
10
10
11
10
Frequency (Hz)
10
12
87 GHz HBT master-slave latch UCSB
PK Sundararajan,
Zach Griffith
InAlAs /InGaAs/InP MESA DHBT
400 Å base, 2000 Å collector,
9 V BVCEO
200 GHz ft, 180 GHz fmax
2.5 x 105 A/cm2 operation
87 GHz input, 43.5 GHz output
-0.06
-0.08
V
out
(Volts)
-0.1
-0.12
-0.14
-0.16
-0.18
-0.2
22
22.02 22.04 22.06 22.08
time (nsec)
22.1
22.12 22.14
8 GHz S ADC
Technology
0.7 um InP MESA DHBT
400 Å base, 2000 Å collector,
9 V BVCEO,
200 GHz ft, 180 GHz fmax
2.5 x 105 A/cm2 operation
Design
simple 2nd-order gm-C topology
comparator is 87 GHz MSS latch
integration by capacitive loads
3-stage comparator, RTZ gated DAC
PK Sundararajan
Results
133 dB (1 Hz) SNR at 74 MHz
equivalent to ~8.8 bits at 200 MS/s
975 kHz FFT bin size
8 GHz clock rate
65.5 MHz signal
64:1 oversampling ratio
Very strong features of SiGe-bipolar transistors
High current density
10 mA/mm2
T-shaped polysilicon emitter
0.25 mm junction
wide contact
low resistance, high yield
Thin intrinsic base: low b
Thick extrinsic base: low Rbb
Low Ccb collector junction
collector pedestal
CVD/CMP SiO2 planarization
regrown poly extrinsic base
High-yield, planar processing
high levels of integration
LSI and VLSI capabilities
SiGe clock rates up to 65 GHz
Much more complex ICs than feasible in InP HBT
InP HBT must reach higher integration scales or will cease to compete
InP vs Si/SiGe HBTs: materials vs scaling advantages
Advantages of InP
~20:1 lower base sheet resistance,
~5:1 higher base electron diffusivity
~3:1 higher collector electron velocity,
~4:1 higher breakdown-at same f.
Disadvantage of InP: archaic mesa fabrication process
Presently only scaled to ~ 1 um (production)
large emitters, poor emitter contact:
low current density: 2 mA/um2
high collector capacitance
nonplanar device - low yield
low integration scales
InP HBT limits to yield: non-planar process
Emitter contact
Failure
modes
liftoff failure:
emitter-base
short-circuit
emitter
base contact
base
base
sub collector
S.I. substrate
sub collector
S.I. substrate
Etch to base
base
excessive
emitter undercut
sub collector
base contact
S.I. substrate
base
Liftoff base metal
base contact
emitter
contact
sub collector
base contact
S.I. substrate
base
sub collector
S.I. substrate
planarization failure: interconnect breaks
Emitter planarization, interconnects
base
base
sub collector
S.I. substrate
sub collector
S.I. substrate
Yield degrades as emitters are
scaled to submicron dimensions
MBE growth of Polycrystalline n+ InAs
Dennis Scott
SiGe HBT process: extensive use of non-selective-area poly-Si regrowth
Can a similar technology be developed for InP ?
Polycrystalline InAs grown on SiN:
• Doping = 1.3 1019 cm-3,
Mobility = 620 cm2/V•s
Poly InAs:Si Doping vs. Temp
19
2.2 10
2 10
• doping-mobility product
81021 (V •s •cm)-1
19
1.8 10
19
Doping
InGaAs lattice matched to InP:
• Doping = 1.0 1019 cm-3,
Mobility = 2200 cm2/V•s
• doping-mobility product
221021 (V •s •cm)-1
19
1.6 10
19
1.4 10
19
1.2 10
1 10
19
8 10
18
6 10
18
945
950
955
960
965
Temp
970
975
980
Polycrystalline InAs has potential as an extrinsic emitter contact
985
1) Epitaxial Growth,
Fe implant isolation
Process Flow:
Single-polyregrowth
InP HBT
2) Deposit Pd/W base Ohmics.
Encapsulate with Si3N4
Etch base-collector junction
base
N- collector
N- collector
N+ subcollector
N+ subcollector
S.I. substrate
S.I. substrate
top view
extrinsic
emitter
and
contact
subcollector
isolation
implant
mask
4) Regrow polycrystalline emitter.
Deposit emitter metal.
Etch through emitter
emitter contact
regrown
InAlAs/InAs
emitter*
Si N
3 4
base contact
Si N
3 4
base
contact
N- collector
N+ subcollector
S.I. substrate
collector
contact
base
contact
base
contact
Si N
3 4
base
3) Passivate with Si3N4
Etch emitter window through base
Form emitter SiN sidewalls
emitter
junction
Dennis Scott
N- collector
N+ subcollector
S.I. substrate
5) Recess etch and deposit
collector contacts
N- collector
N+ subcollector
S.I. substrate
emitter contact
regrown
InAlAs/InAs emitter*
Si N
3 4
base contact
collector
contact
*monocrystalline where
grown on semiconductor,
polycrystalline where
grown on silicon nitride
Regrown-Poly-InAs-Emitter HBT
1
1.0 10
AE = 0.8 x 15 um
2
I b = 100uA/step
0
0
6.0 10
c
I (mA)
8.0 10
0
4.0 10
0
2.0 10
0
0.0 10
0
1
2
3
4
V (V)
ce
Ib, Ic (mA)
2
10
2
10
1
10
0
10
-1
10
-2
10
-3
10
-4
Gummel for 0.8x15 um Emitter
Ic
Ib
0
0.2
0.4
0.6
0.8
Vbe (volts)
1
1.2
Dennis Scott
Emitter Regrowth with Buried Base Contact Metal
Buried W/Au base metal under emitter
→ further reduced Rbb
Similar to buried WSi base contact process (SiGe, Washio)
Dennis Scott
Submicron Scaling of InP HBTs
InP HBTs are a mixed-signal, not a MIMIC technology
for MIMICs, sub-0.1-mm InP HEMTs are hard to beat
mixed-signal is fiber ICs, ADCs, DACs, digital frequency synthesis
these are 1000 -- 40,000 transistor ICs
InP HBTs are struggling to compete with SiGe HBT
application demands transistor counts near/beyond yield limits
large emitter junctions→ high current → power near acceptable limits
no decisive speed advantage in relevant circuits: digital logic
materials advantages being squandered by inadequate scaling
Critically needed for InP HBTs
highly scaled process: 0.2 mm emitters, 0.4 mm collectors
highly planar and high-yield fabrication processes
small emitter junctions (0.2 mm x 0.5 mm) for acceptable power