Transcript Title of Talk - University of California, Santa Barbara

ISSCC 2003 Special Topic Session: Circuits in Emerging Technologies, February 9, San Francisco
Indium Phosphide
Bipolar Integrated Circuits:
40 GHz and beyond
Mark Rodwell
University of California, Santa Barbara
[email protected] 805-893-3244, 805-893-3262 fax
Applications of InP HBTs
Optical Fiber Transceivers
40 Gb/s:
InP and SiGe HBT both feasible
ICs now available; market has vanished
80 & 160 Gb/s may come in time
within feasibility for scaled InP HBT
world may not need capacity for some time
WDM might be better use of fiber bandwidth
1
mmWave Transmission
1 km
Sea level
65-80 GHz, 120-160 GHz, 220-300 GHz Links
Low atmospheric attenuation (weather permitting).
High antenna gains (short wavelengths).
10 Gb/s transmission over 500 meters with 20 cm
antennas needs 4 mW transmitter power
59-64 GHz LANs: short range, wideband, broadcast
Log Transmission
0.1
0.01
1E-3
1E-4
1E-5
1E-6
0.0
Mixed-Signal ICs for Military Radar/Comms
direct digital frequency synthesis, ADCs, DACs
high resolution at very high bandwidths sought
0.2
0.4
0.6
Frequency, THz
0.8
1.0
Motivation for InP HBTs
Parameter
InP/InGaAs
collector electron velocity 3E7 cm/s
base electron diffusivity
40 cm2/s
base sheet resistivity
500 Ohm
comparable breakdown fields
Si/SiGe
1E7 cm/s
~2-4 cm2/s
5000 Ohm
benefit (simplified)
lower tc , higher J
lower tb
lower Rbb
Consequences, if comparable scaling & parasitic reduction:
~3:1 higher bandwidth at a given scaling generation
~3:1 higher breakdown at a given bandwidth
Problem for InP: SiGe has much better scaling & parasitic reduction
Technology comparison today:
Production SiGe and InP have comparable speed
SiGe has much higher integration scales
Production 1 mm InP: low NRE, fast design cycle for SSI/MSI ICs to ~90 GHz
(cost includes design time as well as $/mm2
Present efforts in InP research community
Development of low-parasitic, highly-scaled, high-yield fabrication processes
InP HBT fabrication processes today
Mesa processes with self-aligned base contacts:
Research labs
Moderately low yield → 1000 HBTs/IC
300 GHz ft, 400 GHz fmax , 7 V BVCEO, 100 GHz clock
~ 0.5 mm emitter width
Mesa processes with non-self-aligned base contacts:
Production in GaAs HBT foundries (cell phone power amps)
Somewhat better yield → 3000 HBTs/IC (?)
150 GHz ft, 180 GHz fmax , 7 V BVCEO, 70-90 GHz clock
0.8 mm emitter width,
1.0 $/mm2
Exotic research processes for reduced Ccb:
1) transferred-substrate,
2) strongly undercut collector mesa
technology demonstrations, not IC technologies
Present research processes in InP community:
early development phases
combine InP materials advantages with SiGe-like processes
junction regrowth, dielectric sidewalls,
trenches, pedestal implants…
…more detail in later slides
Scaling
Required transistor design changes required to double transistor bandwidth
key device parameter
required change
collector depletion layer thickness
decrease 2:1
base thickness
decrease 0.707:1
emitter junction width
decrease 4:1
collector junction width
decrease 4:1
emitter resistance per unit emitter area
decrease 4:1
current density
increase 4:1
base contact resistivity
(if contacts lie above collector junction)
decrease 4:1
base contact resistivity
(if contacts do not lie above collector junction)
unchanged
(C ’s, t ’s, I/C ’s all reduced 2:1)
WE
WEB
LE
emitter
base
x
…easily derived by basic geometric calculations
base
collector
WC
WBC
Parasitic Reduction
At a given scaling generation, intelligent choice of device geometry
reduces extrinsic parasitics
wide emitter contact: low resistance
narrow emitter junction: scaling (low Rbb/Ae)
thick extrinsic base : low resistance
thin intrinsic base: low transit time
wide base contacts: low resistance
narrow collector junction: low capacitance
P base
SiO2
N-
N+ subcollector
Much more fully developed in Si…
SiO2
Electronics
for GigaHertz Communication
Optical Transmitters / Receivers are Mixed-Signal ICs
Wideband Optical Transceiver
address
detect
O/E, E/O interfaces
buffer
A
DMUX
D
PLL
Switch
route
clock
MUX
Wideband mm-Wave Transceiver
TIA: small-signal
mm-wave interfaces LIA: often limiting
A
D
Rc
Rc
PLL
I
Q
power
amplifier
Q1
DMUX
D
Rf
Q2
DMUX
I
Q
A
Rf
Q2
I2
I2
I1
I
Q
Q1
electronic
MUX/CMU & DMUX/CDR:
or optical
mostly digital
D
A
I
MUX
Switches:
network protocols,
digital control, fast ICs,
optical, electronic switches
I1 D
A
Q
Small-signal cutoff frequencies (ft , fmax) are ~ predictive of analog speed
Limiting and digital speed much more strongly determined by (I/C) ratios
InP HBT has been well-optimized for ft & fmax, less well for digital speed
How do we improve gate delay ?
Gate Delay Determined by :
Depletion capacitanc e charging
through the logic swing
 VLOGIC 

Ccb  Cbe,depletion 
 IC 
Depletion capacitanc e charging
through the base resistance
Rbb Ccb  Cbe,depletion 
Supplying base  collector
stored charge
through the base resistance
 IC 

Rbb t b  t c 
 VLOGIC 
The logic swing must be at least
 kT

VLOGIC  6
 Rex I c 
 q

out
out
in
in
clock
clock
clock
clock
Delay not well correlated with ft .
VLOGIC
I C Ccb  Cbe,depl  is 60% - 80% of total.
High I C / Ccb  is a key HBT design objective.
 Acollector  TC 





 Aemitter  2veffective 
Rex must be very low for low Vlogic at high J e
Ccb VLOGIC VLOGIC

IC
2VCE ,min
InP logic barely faster tha n SiGe :
need to design for clock speed, not ft & f max
Why isn't base+collector transit time so important ?
Diffusion capacitanc e :
Q base  (t b  t c )I C
 (t b  t c )
Vout(t)
Vout
Vin
t
(t b  t c ) I C
Vbe
kT / q
...active only over kT / q voltage swing.

Under Large - Signal Operation :
Q base  (t b  t c ) I C

t
Vin(t)
diffusion
+ depletion
capacitance
only depletion
capacitance
dI C
Vbe
dVbe
(t b  t c ) I dc
V LOGIC
VLOGIC
Large - signal diffusion capacitanc e
reduced by ratio of
 VLOGIC

 kT / q

, which is ~ 10 : 1

Depletion capacitances present over full voltage swing, no large-signal reduction
Scaling Laws, Collector Current Density, Ccb charging time
Collector Field Collapse (Kirk Effect)
Vcb    ( J / vsat  qN d )(Tc2 / 2 )
base
emitter
sub
collector
collector
Collector Depletion Layer Collapse
Vcb,min    (qN d )(Tc2 / 2 )
base
emitter
sub
collector
collector
 J max  2vsat (Vcb  Vcb,min  2 ) / Tc2
Note that Vbe   , hence (Vcb   )  Vce
Ccb VLOGIC / I C  Acollector Tc VLOGIC
VLOGIC  Acollector  TC 



IC  
VCE  VCE ,min   Aemitter  2vsat 
Collector capacitance charging time is reduced
by thinning the collector while increasing current
Challenges with Scaling:
Collector-base scaling
Mesa HBT: collector under base Ohmics.
Base Ohmics must be one transfer length → sets minimum size for collector
Solution: reduce base contact resistivity → narrower base contacts allowed
Solution: decouple base & collector dimensions
e.g. buried SiO2 in junction (SiGe)
Emitter Ohmic Resistivity:
must improve in proportion to square of speed improvements
Current Density:
self-heating, current-induced dopant migration, dark-line defect formation
Loss of breakdown
avalanche Vbr never less than collector bandgap (1.12 V for Si, 1.4 V for InP)
….sufficient for logic, insufficient for power
Yield
submicron InP processes have progressively decreasing yield
Technology Roadmaps for 40 / 80 / 160 Gb/s
Parameter
Mesa HBT
Generation 1
62 GHz
Mesa HBT
Generation 2
125 GHz
Mesa HBT
Generation 3
237 GHz
Emitter Junction Width
Parasitic Resistivity
1 mm
50 -mm2
0.8 mm
20 -mm2
0.2 mm
5 -mm2
Base Thickness
Doping
Sheet resistance
Contact resistance
400Å
5 1019 /cm2
750 
150 -mm2
300Å
7 1019 /cm2
700 
20 -mm2
250Å
1020 /cm2
700 
10 -mm2
Collector Width
Collector Thickness
Current Density
Acollector/Aemitter
3 mm
3000 Å
1 mA/mm2
4.55
1.6 mm
2000 Å
2.3 mA/mm2
2.6
 mm
1000 Å
9.3 mA/mm2
2.6
ft
170
260
500
f max
170
440
700
C cb / I c
1.7 ps/V
0.63 ps/V
0.31 ps/V
C cb Vlogic / I c
0.5 ps
0.19 ps
0.093 ps
Rbb /(Vlogic / I c )
0.8
0.65
0.52
C je (Vlogic / I C )
1.7 ps
0.72 ps
0.18 ps
Rex /(Vlogic / I c )
0.1
0.15
0.15
Simulated MS-DFF
speed (no interconnects)
M Dahlstrom (UCSB/ONR), Amy Liu (IQE)
InP-collector DHBTs: Self-Aligned Mesa Structure
0.7 um base contact width
200 nm InP collector,
30 nm InGaAs base
8(1019) /cm3 base doping
0.3 um base contact width
1 mm base contacts,
0.5 mm x 7.5 mm emitter junction
0.7 mm emitter contact
emitter junction area: 0.44 mm x 7.4 mm
Collector
I step = 50 uA
/ Emitter Ratio: 2.0 um / 0.5 um, 1.2 um / 0.5 um
B
30
5
3
2.5
4
Vbr,ceo=7 V
2
U
1
0.5
0
2
0
1
2
3
4
5
6
7
Gains (dB)
C
I (mA)
1.5
3
Vce=1.7 V
J=3.7E5 A/cm2
25
20
15
f =282 GHz
8
t
10
f
H
21
>400 GHz
max
1
5
0
0
0.5
1
1.5
V (V)
CE
2
2.5
3
0
10
10
11
10
Frequency (Hz)
10
12
UCSB/ONR: Miguel Urteaga
Submicron InAlAs/InGaAs HBTs:
High power gains at very high frequencies
40
transferred-substrate device
6-40, 75-110, 140-220 GHz
U
30
unbounded U
Gains, dB
S22
20
MSG
10
h
V
ce
0
S11
freq (6.000GHz to 40.00GHz)
freq (75.00GHz to 110.0GHz)
freq (140.0GHz to 220.0GHz)
21
S21
= 1.1 V, I =5 mA
S12*25
c
0.3 mm x 18 mm emitter,
0.7 mm x 18.6 mm collector
10
10
11
10
12
-6
-4
-2
0
2
4
10
Frequency, Hz
Gains are high at 220 GHz, but fmax can’t be extrapolated
freq (6.000GHz to 40.00GHz)
freq (75.00GHz to 110.0GHz)
freq (140.0GHz to 220.0GHz)
6
UCSB/ONR: S. Lee
InP-Collector Double Heterojunction Bipolar Transistors
2
40
I step = 20 mA
fmax = 460 GHz
ft = 139 GHz
b
Gains (dB)
IC (mA)
30
1
VBR,CEO = 8 V @ JE =5*104 A/cm2
2
4
VCE (V)
6
20
343
395
10
0
0
U
8
h21
139
462
0
1
10
100
1000
Frequency (GHz)
0.5 mm x 8 mm emitter (mask)
0.4 mm x 7.5 mm emitter (junction)
1.0 mm x 8.75 mm collector
3000 Å collector drift region
transferred-substrate process
UCSB/ARO: Y. Wei
Large-Area (High Current) DHBTs for mm-Wave Power
8-finger device: 1 x 16 mm emitter, 2 x 20 mm collector
140
2
A =128>um
VBR,CBO
7V
E
120
14
12
10
80
Ic, m A
Ic, mA
100
60
8
6
4
40
2
0
-1
20
0
1
2
3
4
5
6
7
Vcb, V
0
0
2
4
30
U, MSG/MAG, dB
Key challenges with high-current HBTs:
- thermal stability (ballasting)
- minimal base feed metal parasitic resistance
- reliable electromagnetic models of feed networks
8
10
AE=128um2
25
IC=100mA
20
15
6
Vcb, V
Vcb=2.9V
MSG/MAG
U
10
5
0 0
10
fmax=330 GHz
10
1
10
2
Frequency, GHz
10
3
UCSB/ONR: Young-Min Kim
InP/InGaAs/InP Metamorphic DHBTs on GaAs substrates
14
12
3 10
5
2 10
5
1 10
5
8
6
4
2
C
5
J (A/cm )
I (mA)
10
4 10
2
0
0
0
1
2
3
V
CE
4
5
6
(V)
35
U
30
h
Gains (dB)
25
Comparable performance
to lattice-matched of similar design.
21
20
15
f, f
t
max
= 200 GHz
Potential for SSI/MSI InP HBTs
in cheap GaAs HBT foundry
processes.
10
5
0
1
10
100
Frequency (GHz)
1000
UCSB/ONR: Miguel Urteaga
174 GHz, 6.3 dB, Single-Transistor Amplifier
10
S21
S11
S22
50
0.2pF
5
80
1.2ps
30
0.2ps
80
1.2ps
50
30
1.2ps
0
50

0.6ps
dB
IN
OUT
-5
-10
-15
-20
140
150
160
170
180
Freq. (GHz)
0.3 um transferred-substrate HBT
190
200
210
220
UCSB/ONR: Miguel Urteaga
Multi-Stage 140-220 GHz Amplifiers
20
S21
S11
S22
Three-stage amplifier designs:
10
0
dB
12.0 dB gain at 170 GHz
8.5 dB gain at 195 GHz
Cascaded 50  stages with interstage
blocking capacitors
-10
-20
-30
140
150
160
170
180
190
200
210
220
frequency (GHz)
20
S21
S11
S22
10
dB
0
-10
-20
Cell Dimensions: 1.6 mm x 0.59 mm
0.3 um transferred-substrate HBT
-30
140
150
160
170
180
190
frequency (GHz)
200
210
220
UCSB/ARO: Y. Wei
75 GHz, 80 mW Power Amplifier
20
10
P
out
15
CSiN=44fF
0.15 pS
42
CSiN=15fF
2.6 pS
17
Gain
6
10
out
0.31 pS
17
CSiN=92fF
0.38 pS
50
0.58 pS
37
CSiN=15fF
4
P
CSiN=44fF
5
Gain (dB)
PAE (%)
2.3 pS
42
0.58 pS
37
(dBm)
0.38 pS
50
CSiN=92fF
8
2
PAE
0
-5
0
5
10
P (dBm)
0
15
in
0.4  0.9 mm die,
AE = 16 x (1mm x 16 mm)
= 256 mm2
transferred-substrate process
Bias: Ic=130 mA, Vce=4.5 V
250-500 mW is feasible; UCSB designs are constrained by yield difficulties with large # of fingers
UCSB/ONR: PK Sundararajan
87 GHz HBT static frequency divider
InAlAs /InGaAs/InP MESA DHBT
400 Å base, 2000 Å collector,
9 V BVCEO
200 GHz ft, 180 GHz fmax
2.5 x 105 A/cm2 operation
87 GHz input, 43.5 GHz output
-0.06
-0.08
V
out
(Volts)
-0.1
-0.12
-0.14
-0.16
-0.18
-0.2
22
22.02 22.04 22.06 22.08
time (nsec)
22.1
22.12 22.14
InPhi slides
InPhi slides
OC-768 Linear Components
Transimpedance Amplifier
26 dB Limiting Amplifier
Transimpedance (dB ohms)
(single-ended)
Vetury, Pullela, Rodwelll
curves with, without
PIN parasitics
Jaganathan & Pullela
43 Gb/s
Frequency (GHz)
-7.8 dBm sensitivity @ 10-12 BER
(231-1) PRBS
Design Challenges: Gain flatness
Peaking due to interconnect inductance,
gm element phase shift, Ccb variation,
photodiode parasitics,
single-ended / differential converter.
K. Krishnamurti et al
OC-768 Modulator Driver
Vcc
DOUTP
Vxpp
DINP
cell-1
DINN
TAS
TIS
TAS
cell-n
cell-10
DA
Vxpn
Vcc
30 dB gain, 40 GHz bandwidth, >10 dB S11 & S22
8 ps rise/fall (20-80%) , ~0.9 ps RMS jitter
3 Vpp single ended output, 6 V differential
DOUTN
Design Issues: Gain flatness
Distributed line losses, current handling & loaded Z0
Complexity of transmission-line layout
Associated low-frequency droop
Emitter follower negative resistance → peaking
Efficacy of bypass capacitances
Common-mode traveling-wave instability
4:1 Multiplexer / CMU
OC-768 Digital Components
DI0
4:1
MUX
FF
Amp
DO
Buf
ClkOut
DI3
Timing
Control
Lock
Detect
LockDet
PFDO
1:4 Demultiplexer / CDR
Vcon
(recovered 10 Gb/s data)
OFFSET
SENSE Output
5 GHz clock
Limiting
amplifier
Differential
Data Inputs
1:2
DEMUX
+P.D
DP
2:4
DEMUX
DN
10 Gb/s
Differential
Data outputs
4 x 10 Gb/s
50
AGND
Timing
Timing
Control
Sel
622M hz
PI
Filter
C1
PFD
VEE
VCO
47 Gb/s
VCO
PFD
DCKI
Disable
Lock
Detect
VEEA
Ref Clk inputs (622M Hz)
Lock_Ref
Lock Detect
Very strong features of SiGe-bipolar transistors
High current density
10 mA/mm2
T-shaped polysilicon emitter
0.25 mm junction
wide contact
low resistance, high yield
Thin intrinsic base: low tb
Thick extrinsic base: low Rbb
Low Ccb collector junction
collector pedestal
CVD/CMP SiO2 planarization
regrown poly extrinsic base
High-yield, planar processing
high levels of integration
LSI and VLSI capabilities
SiGe clock rates up to 65 GHz
Much more complex ICs than feasible in InP HBT
InP HBT must reach higher integration scales or will cease to compete
Submicron InP HBT
Development: Research
Planar HBT: Dielectric Sidewall Process
sputter & dry-etched
W emitter contact,
dry-etched emitter
emitter-base separation
by dielectric sidewall
Objective: speed
extrinsic parasitic reduction
deep submicron scaling
near-planar
base mesa etched
only to collector
Objective: yield
planar process
eliminate liftoff
eliminate undercut etches
Target Applications:
High speed (>100 GHz) digital
& mixed signal.
160 Gb/s optical fiber transmission
Similar research efforts
Rockwell/GCS/UCSB
Vitesse. Lucent. TRW. HRL Labs.
base contact width
defined by dielecric
sidewall
implant or
trench isolation
-eliminates mesas
N- collector
N+ subcollector
S.I. substrate
Double-poly (SiGe-like) HBT
emitter contact
regrown emitter *
Si N
3 4
base contact
regrown
extrinsic base*
collector
contact
Si N
3 4
N+ subcollector
S.I. substrate
intrinsic base*
N- collector
InP HBTs
InP has better electron transport than SiGe
→ faster if comparable-quality fabrication processes are employed.
Adaptation of 1-mm GaAs (cell phone) HBT foundry process to InP
→ Inexpensive, low NRE, low mask cost, fast design cycle
Good process for SSI/MSI optical fiber and mm-wave ICs
Not good for larger-scale digital / mixed-signal ICs
Conventional but more highly scaled InP HBT processes
→ millimeter-wave power to 200 GHz, perhaps beyond.
Future markets ?
Present efforts in InP research community
low-parasitic, highly-scaled, high-yield fabrication processes
→ 3:1 higher bandwidth at a given scaling generation
→ 3:1 higher breakdown at a given bandwidth
Substantial risk of failure, substantial benefit if successful.