Transcript ATLAS pixel detector opto-electronics - Physics

Radiation-Hard ASICs for Optical Data
Transmission in the ATLAS Pixel
Detector
Richard Kass
The Ohio State University
K.E. Arms, K.K. Gan, M. Johnson, H. Kagan, R. Kass, A. Rahimi,
C. Rush, S. Smith, R. Ter-Antonian, M.M. Zoeller
The Ohio State University
A. Ciliox, M. Holder, S. Nderitu, M. Ziolkowski
Universitaet Siegen, Germany
OUTLINE
Introduction
ASIC description
Opto-board prototype results
Proton irradiation results
Summary
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ATLAS Pixel Detector
2 disks
2 barrel layers
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Inner most charged particle tracking
Pixel size 50mm by 400 mm
Over 100 million sensors
Barrel layers at r = 5.1 and 12.3 cm
Disks at z = 50 and 65 cm
Dosage after 10 years:
– optical link 30 Mrad or 6 x 1014 1-MeV neq/cm2
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ATLAS Pixel Opto-link
VCSEL: Vertical Cavity Surface Emitting Laser diode
VDC:
VCSEL Driver Circuit
PIN:
PiN diode
DORIC: Digital Optical Receiver Integrated Circuit
Opto-board: Holds VDCs, DORICs, PINs, VCSELS
Uses BeO as substrate
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VCSEL Driver Circuit Specs

Convert LVDS input signal into single-ended signal appropriate to
drive the VCSEL diode

Output (bright) current: 0 to 20 mA,
controlled by externally controllable current (Iset)

Standing (dim) current: ~ 1 mA for
fast off-to-on switching of VCSEL

Rise & fall times: 1 ns nominal
(40 MHz signals)
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Duty cycle: (50 ± 4)%

“On” voltage of VCSEL: up to 2.3 V at 20 mA for 2.5 V supply
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Constant current consumption balanced between ON and OFF state

Current design uses TRUELIGHT “high power oxide” VCSELs
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Digital Optical Receiver IC Specs
Decode Bi-Phase Mark encoded (BPM) clock and
command
signals from PIN diode

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Input signal step size:
40 mA to 1000 mA
Extract 40MHz clock

Duty cycle: (50 ± 4)%

Total timing error: < 1ns

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
40MHz
clock
Data
BPM
Bit Error Rate (BER):
< 10-11 at end of life
Compatible with common
cathode PIN array
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VDC/DORIC-I5e Measurements
 Chips are produced using IBM 0.25mm CMOS with enclosed layout
transistors and guard rings. 4 channels per chip.
Detailed measurements of electrical parameters including rise/fall times,
duty cycle, PIN current thresholds, VCSEL drive current …
50
Current (m A)
 DORIC: Minimum PIN current for no bit
error significantly better than spec of
40 mA
spec
40
30
20
10
IVCSEL (mA)
 VDC: dim current is ~ 1 mA as
expected
 VDC: Bright current saturates  14 mA.
– Varies depending on VCSEL V-I
characteristics
– Target is 20 mA, but 14 mA is
enough for annealing to recover
from irradiation damage
0
ISet vs. IVCSEL
1
2
3
4 Link 5
6
7
30
25
20
15
10
5
0
0
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0.5
1
Iset(mA)
1.5
2
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The Opto-board
• Optical signal  electrical signal conversion occurs here
• Contains 7 optical links, each link serving one Pixel module
• Fabricated in 2 flavors
– Layer B: for inner barrel, two data link per module for high occupancy
– Layer D: for outer barrel and disks 1 and 2
80 B boards
• Fabricated with BeO for heat management
430 D boards
– initial prototypes with FR4 for fast turn around and cost saving
Housing
Opto-pack
VCSEL
array
Pin array
VDC
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DORIC
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Opto-board Performance & Status
• Detailed measurements are done on all critical electrical and optical
parameters to check performance/quality
– LVDS rise/fall times, jitter…,
– Optical power, optical rise/fall times, duty cycle…
– The opto-boards meet or exceed all the pixel detector requirements
2000
Power (mW)
Power (mW)
Optical power
1500
1000
Optical power at 10 mA
significantly above spec
spec
500
0
1
2
3
4
Channel
5
6
7
• 28 boards were delivered for detailed testing
– Equal number of layers B and disks
– no known circuit design error but a few SMDs detached from 3 boards in transit
• Received 80 B-layer opto-boards with layout changes to improve adhesion
– populated a board and it works fine
• Will order 430 boards for outer barrel and disks in November
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Radiation Hardness Measurements
• Important to measure/certify radiation hardness of ASICs
and opto-board and its components:
– VCSEL and PIN arrays
– VDC and DORIC chips
– Encapsulant, fibers, glues, etc.
• Use CERN’s T7 beam (24 GeV Proton) for radiation
hardness studies
– “Cold box” setup: electrical testing of DORIC and VDC
 Exposed up to 62 Mrad
– Shuttle setup: testing of optical links on opto-boards
using DORIC and VDC
 Can be moved in and out of beam remotely for VCSEL annealing
 Exposed up to 32 Mrad
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Real Time Monitoring in Beam Test
Real time testing of opto-board system using loop-back setup
25 meter optical
fiber cable
Opto-board
clock
bi-phase marked
optical signal
PIN
decoded data
VCSEL
VDC
decoded clock
VCSEL
VDC
DORIC
Signal routed back to
opto-baord via test
board attached to 80pin connector
data
Bit error test board
In control room
In beam
Compare transmitted and decoded dated
measure minimum PIN current for no bit errors
Measure optical power
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Setup for Irradiation in Shuttle at CERN
OSU
Shuttle test
electronics prior to
shipping to CERN
25 meter optical fiber
Opto-boards
Rad hard
optical
fibers
CERN T7
Remotely moves
in/out of beam
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CERN T7
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Rise/Fall times, Jitter, and Duty Cycle
optical rise time
LVDS Duty Cycle
1000
Optical
rise time
decoded clock (LVDS) duty cycle
800
50
trise (ps)
+ Duty Cycle (%)
60
40
600
400
200
30
After irrad
0
1
2
3
4
5
6
7
1
3
5
1
9
11
13
Channel
1000
decoded clock (LVDS) Jitter
0.8
7
optical fall tim e
Link
Optical fall time
800
0.6
tfall (ps)
Jitter (ns)
Before irrad
0.4
0.2
0
600
400
200
0
1
2
3
4
5
6
7
1
Link
3
5
7
9
11
13
Channel
• Each plot shows the results for two opto-boards
• No degradation in rise/fall times
• Decoded clock duty cycle and jitter within the limits after irradiation
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PIN Current Threshold vs Dosage
Dosage (Mrad)
4.4
50
10.5
Threshold (m A)
anneal
16.8
anneal
anneal
23.8
30.6
anneal
32.3
anneal
40
30
20
10
0
0
20
40
60
80
100
120
Time (h)
PIN current thresholds for no bit errors remain constant
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Optical Power vs. Dosage
Spec
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Irradiate ~5 Mrad/day (10 hours) with annealing rest of the day
Optical power decreases with dosage as expected due to VCSELs
Limited annealing recovers some lost power
Still acceptable power after 30 Mrad
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Summary
• VDC-I5e and DORIC-I5e meet all the ATLAS/PIXEL specs
– Chip production is completed
• Radiation hardness of DORIC/VDC is adequate for the PIXEL
detector
– VDC/DORIC continue to perform well at ≥ 62 Mrad of 24 GeV protons
• Several pre-production opto-boards have been fabricated
– Meet all the pixel detector requirements
– Excellent optical power
• No degradation in system performance for ≥ 32 Mrad proton
irradiation
– Low PIN current for no bit error
– Annealing recovers most of the lost power
• Start opto-link production in October 2004
– Complete production by September 2005
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Backup Slides
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Status of VDC & DORIC
 Original design for ATLAS SemiConductor Tracker (SCT)
– AMS 0.8 mm BiPolar in radiation tolerant process (4 V)
 DMILL #1-3: Summer 1999 - May 2001
– 0.8 mm CMOS rad-hard process (3.2 V)
– VDC & DORIC #3: meet specs
– severe degradation of circuit performance in April 2001 proton irradiation
 IBM #1-5: Summer 2001 - Dec 2002
– 0.25 mm CMOS rad-hard process (2.5 V)
– enclosed layout transistors and guard rings for improved radiation hardness
 IBM 5e: April 2003 engineering run
– convert 3-layer to 5-layer layout for submission
with pixel Module Control Chip (MCC) for cost saving
 this is the production run since chips meet specs
and sufficient quantity of chips were produced
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VDC Performance
Before irradiation
expected
radiation
dosage
After irradiation
 Current output is constant vs. dosage
 Duty cycle and rise/fall times
consistent before and after irradiation
– Better rise and fall times on the
opto-board due to shorter wire
bonds and traces
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IEEE04/Rome
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DORIC Performance
After irrad
Before irrad
• Threshold for no bit error unchanged
after irradiation
• Jitter consistent before and after
irradiation
• Clock duty cycle slightly out of spec
after irradiation
– Minimum 45.5% (spec 46%)
• Threshold and duty cycle improve with
shorter wire bonds and traces
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Proton Induced Bit Errors in PIN
• Convert bit errors to bit error rates at opto-link
1.E-08
0
100
200
300
400
500
600
1.E-09
BER
Link Number:
1
3
5
7
1.E-10
2
4
6
1.E-11
1.E-12
IPIN (mA)
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•
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Bit error rate decreases with PIN current as expected
Bit error rate: ~3 x 10-10 at 100 mA (1.4 errors/minutes)
– DORIC spec: 10-11
– Opto-link error rate is limited by SEU
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